Merge branch 'master' of git://git.denx.de/u-boot-i2c

[oweals/u-boot.git] / drivers / serial / serial_pl01x.c

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index c0ae9472424541d20343e2ea2185d8202dafe8f1..b331be794badb8f5d84710ba693348ca9600bc2e 100644 (file)
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -30,6 +30,8 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
 #include "serial_pl01x.h"
 
 /*
@@ -47,14 +49,20 @@ static int pl01x_tstc (int portnum);
 unsigned int baudrate = CONFIG_BAUDRATE;
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct pl01x_regs *pl01x_get_regs(int portnum)
+{
+       return (struct pl01x_regs *) port[portnum];
+}
+
 #ifdef CONFIG_PL010_SERIAL
 
-int serial_init (void)
+static int pl01x_serial_init(void)
 {
+       struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
        unsigned int divisor;
 
        /* First, disable everything */
-       writel(0x0, port[CONSOLE_PORT] + UART_PL010_CR);
+       writel(0, &regs->pl010_cr);
 
        /* Set baud rate */
        switch (baudrate) {
@@ -82,15 +90,14 @@ int serial_init (void)
                divisor = UART_PL010_BAUD_38400;
        }
 
-       writel(((divisor & 0xf00) >> 8), port[CONSOLE_PORT] + UART_PL010_LCRM);
-       writel((divisor & 0xff), port[CONSOLE_PORT] + UART_PL010_LCRL);
+       writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
+       writel(divisor & 0xff, &regs->pl010_lcrl);
 
        /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
-       writel((UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN),
-               port[CONSOLE_PORT] + UART_PL010_LCRH);
+       writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);
 
        /* Finally, enable the UART */
-       writel((UART_PL010_CR_UARTEN), port[CONSOLE_PORT] + UART_PL010_CR);
+       writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 
        return 0;
 }
@@ -99,15 +106,25 @@ int serial_init (void)
 
 #ifdef CONFIG_PL011_SERIAL
 
-int serial_init (void)
+static int pl01x_serial_init(void)
 {
+       struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
        unsigned int temp;
        unsigned int divider;
        unsigned int remainder;
        unsigned int fraction;
+       unsigned int lcr;
+
+#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+       /* Empty RX fifo if necessary */
+       if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
+               while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
+                       readl(&regs->dr);
+       }
+#endif
 
        /* First, disable everything */
-       writel(0x0, port[CONSOLE_PORT] + UART_PL011_CR);
+       writel(0, &regs->pl011_cr);
 
        /*
         * Set baud rate
@@ -121,23 +138,40 @@ int serial_init (void)
        temp = (8 * remainder) / baudrate;
        fraction = (temp >> 1) + (temp & 1);
 
-       writel(divider, port[CONSOLE_PORT] + UART_PL011_IBRD);
-       writel(fraction, port[CONSOLE_PORT] + UART_PL011_FBRD);
+       writel(divider, &regs->pl011_ibrd);
+       writel(fraction, &regs->pl011_fbrd);
 
        /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
-       writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN),
-               port[CONSOLE_PORT] + UART_PL011_LCRH);
-
+       lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+       writel(lcr, &regs->pl011_lcrh);
+
+#ifdef CONFIG_PL011_SERIAL_RLCR
+       {
+               int i;
+
+               /*
+                * Program receive line control register after waiting
+                * 10 bus cycles.  Delay be writing to readonly register
+                * 10 times
+                */
+               for (i = 0; i < 10; i++)
+                       writel(lcr, &regs->fr);
+
+               writel(lcr, &regs->pl011_rlcr);
+               /* lcrh needs to be set again for change to be effective */
+               writel(lcr, &regs->pl011_lcrh);
+       }
+#endif
        /* Finally, enable the UART */
-       writel((UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE),
-               port[CONSOLE_PORT] + UART_PL011_CR);
+       writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
+              &regs->pl011_cr);
 
        return 0;
 }
 
 #endif /* CONFIG_PL011_SERIAL */
 
-void serial_putc (const char c)
+static void pl01x_serial_putc(const char c)
 {
        if (c == '\n')
                pl01x_putc (CONSOLE_PORT, '\r');
@@ -145,53 +179,59 @@ void serial_putc (const char c)
        pl01x_putc (CONSOLE_PORT, c);
 }
 
-void serial_puts (const char *s)
-{
-       while (*s) {
-               serial_putc (*s++);
-       }
-}
-
-int serial_getc (void)
+static int pl01x_serial_getc(void)
 {
        return pl01x_getc (CONSOLE_PORT);
 }
 
-int serial_tstc (void)
+static int pl01x_serial_tstc(void)
 {
        return pl01x_tstc (CONSOLE_PORT);
 }
 
-void serial_setbrg (void)
+static void pl01x_serial_setbrg(void)
 {
+       struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
+
        baudrate = gd->baudrate;
+       /*
+        * Flush FIFO and wait for non-busy before changing baudrate to avoid
+        * crap in console
+        */
+       while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
+               WATCHDOG_RESET();
+       while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
+               WATCHDOG_RESET();
        serial_init();
 }
 
 static void pl01x_putc (int portnum, char c)
 {
+       struct pl01x_regs *regs = pl01x_get_regs(portnum);
+
        /* Wait until there is space in the FIFO */
-       while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
+       while (readl(&regs->fr) & UART_PL01x_FR_TXFF)
                WATCHDOG_RESET();
 
        /* Send the character */
-       writel(c, port[portnum] + UART_PL01x_DR);
+       writel(c, &regs->dr);
 }
 
 static int pl01x_getc (int portnum)
 {
+       struct pl01x_regs *regs = pl01x_get_regs(portnum);
        unsigned int data;
 
        /* Wait until there is data in the FIFO */
-       while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
+       while (readl(&regs->fr) & UART_PL01x_FR_RXFE)
                WATCHDOG_RESET();
 
-       data = readl(port[portnum] + UART_PL01x_DR);
+       data = readl(&regs->dr);
 
        /* Check for an error flag */
        if (data & 0xFFFFFF00) {
                /* Clear the error */
-               writel(0xFFFFFFFF, port[portnum] + UART_PL01x_ECR);
+               writel(0xFFFFFFFF, &regs->ecr);
                return -1;
        }
 
@@ -200,7 +240,29 @@ static int pl01x_getc (int portnum)
 
 static int pl01x_tstc (int portnum)
 {
+       struct pl01x_regs *regs = pl01x_get_regs(portnum);
+
        WATCHDOG_RESET();
-       return !(readl(port[portnum] + UART_PL01x_FR) &
-                UART_PL01x_FR_RXFE);
+       return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
+}
+
+static struct serial_device pl01x_serial_drv = {
+       .name   = "pl01x_serial",
+       .start  = pl01x_serial_init,
+       .stop   = NULL,
+       .setbrg = pl01x_serial_setbrg,
+       .putc   = pl01x_serial_putc,
+       .puts   = default_serial_puts,
+       .getc   = pl01x_serial_getc,
+       .tstc   = pl01x_serial_tstc,
+};
+
+void pl01x_serial_initialize(void)
+{
+       serial_register(&pl01x_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+       return &pl01x_serial_drv;
 }