+// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright 2019 NXP
* Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
+#include <fsl_lpuart.h>
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
+#include <dm/device_compat.h>
#include <linux/compiler.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#define CTRL_TE (1 << 19)
#define CTRL_RE (1 << 18)
+#define FIFO_RXFLUSH BIT(14)
+#define FIFO_TXFLUSH BIT(15)
+#define FIFO_TXSIZE_MASK 0x70
+#define FIFO_TXSIZE_OFF 4
+#define FIFO_RXSIZE_MASK 0x7
+#define FIFO_RXSIZE_OFF 0
#define FIFO_TXFE 0x80
+#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
+#define FIFO_RXFE 0x08
+#else
#define FIFO_RXFE 0x40
+#endif
-#define WATER_TXWATER_OFF 1
+#define WATER_TXWATER_OFF 0
#define WATER_RXWATER_OFF 16
DECLARE_GLOBAL_DATA_PTR;
+#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
+#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
+
+enum lpuart_devtype {
+ DEV_VF610 = 1,
+ DEV_LS1021A,
+ DEV_MX7ULP,
+ DEV_IMX8,
+ DEV_IMXRT,
+};
+
struct lpuart_serial_platdata {
- struct lpuart_fsl *reg;
+ void *reg;
+ enum lpuart_devtype devtype;
+ ulong flags;
};
-#ifndef CONFIG_LPUART_32B_REG
-static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
+static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
+{
+ if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
+ if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
+ *(u32 *)val = in_be32(addr);
+ else
+ *(u32 *)val = in_le32(addr);
+ }
+}
+
+static void lpuart_write32(u32 flags, u32 *addr, u32 val)
+{
+ if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
+ if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
+ out_be32(addr, val);
+ else
+ out_le32(addr, val);
+ }
+}
+
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 0
+#endif
+
+u32 __weak get_lpuart_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+#if CONFIG_IS_ENABLED(CLK)
+static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
+{
+ struct clk per_clk;
+ ulong rate;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", &per_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get per clk: %d\n", ret);
+ return ret;
+ }
+
+ rate = clk_get_rate(&per_clk);
+ if ((long)rate <= 0) {
+ dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
+ return ret;
+ }
+ *clk = rate;
+ return 0;
+}
+#else
+static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
+{ return -ENOSYS; }
+#endif
+
+static bool is_lpuart32(struct udevice *dev)
+{
+ struct lpuart_serial_platdata *plat = dev->platdata;
+
+ return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
+}
+
+static void _lpuart_serial_setbrg(struct udevice *dev,
+ int baudrate)
{
- u32 clk = mxc_get_clock(MXC_UART_CLK);
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_fsl *base = plat->reg;
+ u32 clk;
u16 sbr;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(CLK)) {
+ ret = get_lpuart_clk_rate(dev, &clk);
+ if (ret)
+ return;
+ } else {
+ clk = get_lpuart_clk();
+ }
sbr = (u16)(clk / (16 * baudrate));
__raw_writeb(sbr & 0xff, &base->ubdl);
}
-static int _lpuart_serial_getc(struct lpuart_fsl *base)
+static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
{
+ struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
WATCHDOG_RESET();
return __raw_readb(&base->ud);
}
-static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
+static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
+ const char c)
{
- if (c == '\n')
- _lpuart_serial_putc(base, '\r');
+ struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & US1_TDRE))
WATCHDOG_RESET();
}
/* Test whether a character is in the RX buffer */
-static int _lpuart_serial_tstc(struct lpuart_fsl *base)
+static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
{
+ struct lpuart_fsl *base = plat->reg;
+
if (__raw_readb(&base->urcfifo) == 0)
return 0;
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int _lpuart_serial_init(struct lpuart_fsl *base)
+static int _lpuart_serial_init(struct udevice *dev)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
u8 ctrl;
ctrl = __raw_readb(&base->uc2);
__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
/* provide data bits, parity, stop bit, etc */
- _lpuart_serial_setbrg(base, gd->baudrate);
+ _lpuart_serial_setbrg(dev, gd->baudrate);
__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
return 0;
}
-static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
+static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
+ int baudrate)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_fsl_reg32 *base = plat->reg;
+ u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
+ u32 clk;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(CLK)) {
+ ret = get_lpuart_clk_rate(dev, &clk);
+ if (ret)
+ return;
+ } else {
+ clk = get_lpuart_clk();
+ }
- _lpuart_serial_setbrg(reg, baudrate);
+ baud_diff = baudrate;
+ osr = 0;
+ sbr = 0;
- return 0;
-}
+ for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
+ tmp_sbr = (clk / (baudrate * tmp_osr));
-static int lpuart_serial_getc(struct udevice *dev)
-{
- struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
+ if (tmp_sbr == 0)
+ tmp_sbr = 1;
- return _lpuart_serial_getc(reg);
-}
+ /*calculate difference in actual buad w/ current values */
+ tmp_diff = (clk / (tmp_osr * tmp_sbr));
+ tmp_diff = tmp_diff - baudrate;
-static int lpuart_serial_putc(struct udevice *dev, const char c)
-{
- struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
+ /* select best values between sbr and sbr+1 */
+ if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
+ tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
+ tmp_sbr++;
+ }
- _lpuart_serial_putc(reg, c);
+ if (tmp_diff <= baud_diff) {
+ baud_diff = tmp_diff;
+ osr = tmp_osr;
+ sbr = tmp_sbr;
+ }
+ }
- return 0;
-}
+ /*
+ * TODO: handle buadrate outside acceptable rate
+ * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
+ * {
+ * Unacceptable baud rate difference of more than 3%
+ * return kStatus_LPUART_BaudrateNotSupport;
+ * }
+ */
+ tmp = in_le32(&base->baud);
-static int lpuart_serial_pending(struct udevice *dev, bool input)
-{
- struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
+ if ((osr > 3) && (osr < 8))
+ tmp |= LPUART_BAUD_BOTHEDGE_MASK;
- if (input)
- return _lpuart_serial_tstc(reg);
- else
- return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
-}
+ tmp &= ~LPUART_BAUD_OSR_MASK;
+ tmp |= LPUART_BAUD_OSR(osr-1);
-static int lpuart_serial_probe(struct udevice *dev)
-{
- struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
+ tmp &= ~LPUART_BAUD_SBR_MASK;
+ tmp |= LPUART_BAUD_SBR(sbr);
+
+ /* explicitly disable 10 bit mode & set 1 stop bit */
+ tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
- return _lpuart_serial_init(reg);
+ out_le32(&base->baud, tmp);
}
-#else
-static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
+static void _lpuart32_serial_setbrg(struct udevice *dev,
+ int baudrate)
{
- u32 clk = CONFIG_SYS_CLK_FREQ;
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_fsl_reg32 *base = plat->reg;
+ u32 clk;
u32 sbr;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(CLK)) {
+ ret = get_lpuart_clk_rate(dev, &clk);
+ if (ret)
+ return;
+ } else {
+ clk = get_lpuart_clk();
+ }
sbr = (clk / (16 * baudrate));
/* place adjustment later - n/32 BRFA */
- out_be32(&base->baud, sbr);
+ lpuart_write32(plat->flags, &base->baud, sbr);
}
-static int _lpuart32_serial_getc(struct lpuart_fsl *base)
+static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
{
- u32 stat;
+ struct lpuart_fsl_reg32 *base = plat->reg;
+ u32 stat, val;
- while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
- out_be32(&base->stat, STAT_FLAGS);
+ lpuart_read32(plat->flags, &base->stat, &stat);
+ while ((stat & STAT_RDRF) == 0) {
+ lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
WATCHDOG_RESET();
+ lpuart_read32(plat->flags, &base->stat, &stat);
}
- return in_be32(&base->data) & 0x3ff;
+ lpuart_read32(plat->flags, &base->data, &val);
+
+ lpuart_read32(plat->flags, &base->stat, &stat);
+ if (stat & STAT_OR)
+ lpuart_write32(plat->flags, &base->stat, STAT_OR);
+
+ return val & 0x3ff;
}
-static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
+static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
+ const char c)
{
+ struct lpuart_fsl_reg32 *base = plat->reg;
+ u32 stat;
+
if (c == '\n')
- _lpuart32_serial_putc(base, '\r');
+ serial_putc('\r');
+
+ while (true) {
+ lpuart_read32(plat->flags, &base->stat, &stat);
+
+ if ((stat & STAT_TDRE))
+ break;
- while (!(in_be32(&base->stat) & STAT_TDRE))
WATCHDOG_RESET();
+ }
- out_be32(&base->data, c);
+ lpuart_write32(plat->flags, &base->data, c);
}
/* Test whether a character is in the RX buffer */
-static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
+static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
{
- if ((in_be32(&base->water) >> 24) == 0)
+ struct lpuart_fsl_reg32 *base = plat->reg;
+ u32 water;
+
+ lpuart_read32(plat->flags, &base->water, &water);
+
+ if ((water >> 24) == 0)
return 0;
return 1;
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int _lpuart32_serial_init(struct lpuart_fsl *base)
+static int _lpuart32_serial_init(struct udevice *dev)
{
- u8 ctrl;
-
- ctrl = in_be32(&base->ctrl);
- ctrl &= ~CTRL_RE;
- ctrl &= ~CTRL_TE;
- out_be32(&base->ctrl, ctrl);
-
- out_be32(&base->modir, 0);
- out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
-
- out_be32(&base->match, 0);
-
- /* provide data bits, parity, stop bit, etc */
- _lpuart32_serial_setbrg(base, gd->baudrate);
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
+ u32 val, tx_fifo_size;
+
+ lpuart_read32(plat->flags, &base->ctrl, &val);
+ val &= ~CTRL_RE;
+ val &= ~CTRL_TE;
+ lpuart_write32(plat->flags, &base->ctrl, val);
+
+ lpuart_write32(plat->flags, &base->modir, 0);
+
+ lpuart_read32(plat->flags, &base->fifo, &val);
+ tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
+ /* Set the TX water to half of FIFO size */
+ if (tx_fifo_size > 1)
+ tx_fifo_size = tx_fifo_size >> 1;
+
+ /* Set RX water to 0, to be triggered by any receive data */
+ lpuart_write32(plat->flags, &base->water,
+ (tx_fifo_size << WATER_TXWATER_OFF));
+
+ /* Enable TX and RX FIFO */
+ val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
+ lpuart_write32(plat->flags, &base->fifo, val);
+
+ lpuart_write32(plat->flags, &base->match, 0);
+
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
+ plat->devtype == DEV_IMXRT) {
+ _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
+ } else {
+ /* provide data bits, parity, stop bit, etc */
+ _lpuart32_serial_setbrg(dev, gd->baudrate);
+ }
- out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
+ lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
return 0;
}
-static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
+static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
-
- _lpuart32_serial_setbrg(reg, baudrate);
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+
+ if (is_lpuart32(dev)) {
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
+ plat->devtype == DEV_IMXRT)
+ _lpuart32_serial_setbrg_7ulp(dev, baudrate);
+ else
+ _lpuart32_serial_setbrg(dev, baudrate);
+ } else {
+ _lpuart_serial_setbrg(dev, baudrate);
+ }
return 0;
}
-static int lpuart32_serial_getc(struct udevice *dev)
+static int lpuart_serial_getc(struct udevice *dev)
{
struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
- return _lpuart32_serial_getc(reg);
+ if (is_lpuart32(dev))
+ return _lpuart32_serial_getc(plat);
+
+ return _lpuart_serial_getc(plat);
}
-static int lpuart32_serial_putc(struct udevice *dev, const char c)
+static int lpuart_serial_putc(struct udevice *dev, const char c)
{
struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
- _lpuart32_serial_putc(reg, c);
+ if (is_lpuart32(dev))
+ _lpuart32_serial_putc(plat, c);
+ else
+ _lpuart_serial_putc(plat, c);
return 0;
}
-static int lpuart32_serial_pending(struct udevice *dev, bool input)
+static int lpuart_serial_pending(struct udevice *dev, bool input)
{
struct lpuart_serial_platdata *plat = dev->platdata;
struct lpuart_fsl *reg = plat->reg;
+ struct lpuart_fsl_reg32 *reg32 = plat->reg;
+ u32 stat;
+
+ if (is_lpuart32(dev)) {
+ if (input) {
+ return _lpuart32_serial_tstc(plat);
+ } else {
+ lpuart_read32(plat->flags, ®32->stat, &stat);
+ return stat & STAT_TDRE ? 0 : 1;
+ }
+ }
if (input)
- return _lpuart32_serial_tstc(reg);
+ return _lpuart_serial_tstc(plat);
else
- return in_be32(®->stat) & STAT_TDRE ? 0 : 1;
+ return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
}
-static int lpuart32_serial_probe(struct udevice *dev)
+static int lpuart_serial_probe(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
- struct lpuart_fsl *reg = plat->reg;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk per_clk;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", &per_clk);
+ if (!ret) {
+ ret = clk_enable(&per_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get per clk: %d\n", ret);
+ return ret;
+ }
+ } else {
+ debug("%s: Failed to get per clk: %d\n", __func__, ret);
+ }
+#endif
- return _lpuart32_serial_init(reg);
+ if (is_lpuart32(dev))
+ return _lpuart32_serial_init(dev);
+ else
+ return _lpuart_serial_init(dev);
}
-#endif /* CONFIG_LPUART_32B_REG */
static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
{
struct lpuart_serial_platdata *plat = dev->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
fdt_addr_t addr;
- addr = dev_get_addr(dev);
+ addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- plat->reg = (struct lpuart_fsl *)addr;
+ plat->reg = (void *)addr;
+ plat->flags = dev_get_driver_data(dev);
+
+ if (fdtdec_get_bool(blob, node, "little-endian"))
+ plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
+
+ if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
+ plat->devtype = DEV_LS1021A;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
+ plat->devtype = DEV_MX7ULP;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
+ plat->devtype = DEV_VF610;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
+ plat->devtype = DEV_IMX8;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
+ plat->devtype = DEV_IMXRT;
return 0;
}
-#ifndef CONFIG_LPUART_32B_REG
static const struct dm_serial_ops lpuart_serial_ops = {
.putc = lpuart_serial_putc,
.pending = lpuart_serial_pending,
};
static const struct udevice_id lpuart_serial_ids[] = {
- { .compatible = "fsl,vf610-lpuart" },
+ { .compatible = "fsl,ls1021a-lpuart", .data =
+ LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
+ { .compatible = "fsl,imx7ulp-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
+ { .compatible = "fsl,vf610-lpuart"},
+ { .compatible = "fsl,imx8qm-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
+ { .compatible = "fsl,imxrt-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ }
};
.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
.probe = lpuart_serial_probe,
.ops = &lpuart_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
-#else /* CONFIG_LPUART_32B_REG */
-static const struct dm_serial_ops lpuart32_serial_ops = {
- .putc = lpuart32_serial_putc,
- .pending = lpuart32_serial_pending,
- .getc = lpuart32_serial_getc,
- .setbrg = lpuart32_serial_setbrg,
-};
-
-static const struct udevice_id lpuart32_serial_ids[] = {
- { .compatible = "fsl,ls1021a-lpuart" },
- { }
-};
-
-U_BOOT_DRIVER(serial_lpuart32) = {
- .name = "serial_lpuart32",
- .id = UCLASS_SERIAL,
- .of_match = lpuart32_serial_ids,
- .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
- .probe = lpuart32_serial_probe,
- .ops = &lpuart32_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
};
-#endif /* CONFIG_LPUART_32B_REG */
projects / oweals / u-boot.git / blobdiff