Merge tag 'efi-2020-07-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

[oweals/u-boot.git] / drivers / ram / stm32mp1 / stm32mp1_ddr_regs.h

diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
index a606b2bcbe27dc9d8ef9da2eb71ebee2be0625f0..3c8885a965770864ebea9b9bfe2b28f72fcde993 100644 (file)
--- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
@@ -7,6 +7,7 @@
 #define _RAM_STM32MP1_DDR_REGS_H
 
 /* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
+#include <linux/bitops.h>
 struct stm32mp1_ddrctl {
        u32 mstr ;              /* 0x0 Master*/
        u32 stat;               /* 0x4 Operating Mode Status*/
@@ -234,6 +235,8 @@ struct stm32mp1_ddrphy {
 
 /* DDRCTRL REGISTERS */
 #define DDRCTRL_MSTR_DDR3                      BIT(0)
+#define DDRCTRL_MSTR_LPDDR2                    BIT(2)
+#define DDRCTRL_MSTR_LPDDR3                    BIT(3)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK       GENMASK(13, 12)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL       (0 << 12)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF       (1 << 12)
@@ -258,6 +261,7 @@ struct stm32mp1_ddrphy {
 
 #define DDRCTRL_MRSTAT_MR_WR_BUSY              BIT(0)
 
+#define DDRCTRL_PWRCTL_SELFREF_EN              BIT(0)
 #define DDRCTRL_PWRCTL_POWERDOWN_EN            BIT(1)
 #define DDRCTRL_PWRCTL_SELFREF_SW              BIT(5)
 
@@ -330,6 +334,7 @@ struct stm32mp1_ddrphy {
 
 #define DDRPHYC_DXNGCR_DXEN                    BIT(0)
 
+#define DDRPHYC_DXNDLLCR_DLLSRST               BIT(30)
 #define DDRPHYC_DXNDLLCR_DLLDIS                        BIT(31)
 #define DDRPHYC_DXNDLLCR_SDPHASE_MASK          GENMASK(17, 14)
 #define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT         14