u32 sdsr; /* SDRAM Status register */
};
+/*
+ * NOR/PSRAM Control register BCR1
+ * FMC controller Enable, only availabe for H7
+ */
+#define FMC_BCR1_FMCEN BIT(31)
+
/* Control register SDCR */
#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
MAX_SDRAM_BANK,
};
+enum stm32_fmc_family {
+ STM32F7_FMC,
+ STM32H7_FMC,
+};
+
struct bank_params {
struct stm32_sdram_control *sdram_control;
struct stm32_sdram_timing *sdram_timing;
struct stm32_fmc_regs *base;
u8 no_sdram_banks;
struct bank_params bank_params[MAX_SDRAM_BANK];
+ enum stm32_fmc_family family;
};
#define SDRAM_MODE_BL_SHIFT 0
u32 ref_count;
u8 i;
+ /* disable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
+
for (i = 0; i < params->no_sdram_banks; i++) {
control = params->bank_params[i].sdram_control;
timing = params->bank_params[i].sdram_timing;
| timing->txsr << FMC_SDTR_TXSR_SHIFT
| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
®s->sdtr2);
+
if (target_bank == SDRAM_BANK1)
ctb = FMC_SDCMR_BANK_1;
else
writel(ref_count << 1, ®s->sdrtr);
}
+ /* enable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ setbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
+
return 0;
}
bank_name = (char *)ofnode_get_name(bank_node);
strsep(&bank_name, "@");
if (!bank_name) {
- error("missing sdram bank index");
+ pr_err("missing sdram bank index");
return -EINVAL;
}
(long unsigned int *)&bank_params->target_bank);
if (bank_params->target_bank >= MAX_SDRAM_BANK) {
- error("Found bank %d , but only bank 0 and 1 are supported",
+ pr_err("Found bank %d , but only bank 0 and 1 are supported",
bank_params->target_bank);
return -EINVAL;
}
sizeof(struct stm32_sdram_control));
if (!params->bank_params[bank].sdram_control) {
- error("st,sdram-control not found for %s",
+ pr_err("st,sdram-control not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
sizeof(struct stm32_sdram_timing));
if (!params->bank_params[bank].sdram_timing) {
- error("st,sdram-timing not found for %s",
+ pr_err("st,sdram-timing not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
return -EINVAL;
params->base = (struct stm32_fmc_regs *)addr;
+ params->family = dev_get_driver_data(dev);
#ifdef CONFIG_CLK
struct clk clk;
};
static const struct udevice_id stm32_fmc_ids[] = {
- { .compatible = "st,stm32-fmc" },
+ { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
+ { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
{ }
};