Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

[oweals/u-boot.git] / drivers / pinctrl / renesas / pfc-r8a7791.c

diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index 81669554597bd75d866a5c51b47909de31c9516a..d6095d6f674c8265765c382264ac3fd5c87a4eef 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -5431,7 +5431,7 @@ static const struct {
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-       { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+       { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
                GP_0_31_FN, FN_IP1_22_20,
                GP_0_30_FN, FN_IP1_19_17,
                GP_0_29_FN, FN_IP1_16_14,
@@ -5463,9 +5463,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_0_3_FN, FN_IP0_3,
                GP_0_2_FN, FN_IP0_2,
                GP_0_1_FN, FN_IP0_1,
-               GP_0_0_FN, FN_IP0_0, }
+               GP_0_0_FN, FN_IP0_0, ))
        },
-       { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+       { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
                0, 0,
                0, 0,
                0, 0,
@@ -5497,9 +5497,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_1_3_FN, FN_IP2_2_0,
                GP_1_2_FN, FN_IP1_31_29,
                GP_1_1_FN, FN_IP1_28_26,
-               GP_1_0_FN, FN_IP1_25_23, }
+               GP_1_0_FN, FN_IP1_25_23, ))
        },
-       { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+       { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
                GP_2_31_FN, FN_IP6_7_6,
                GP_2_30_FN, FN_IP6_5_3,
                GP_2_29_FN, FN_IP6_2_0,
@@ -5531,9 +5531,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_2_3_FN, FN_IP4_4_2,
                GP_2_2_FN, FN_IP4_1_0,
                GP_2_1_FN, FN_IP3_30_28,
-               GP_2_0_FN, FN_IP3_27_25 }
+               GP_2_0_FN, FN_IP3_27_25 ))
        },
-       { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+       { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
                GP_3_31_FN, FN_IP9_18_17,
                GP_3_30_FN, FN_IP9_16,
                GP_3_29_FN, FN_IP9_15_13,
@@ -5565,9 +5565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_3_3_FN, FN_IP7_12_11,
                GP_3_2_FN, FN_IP7_10_9,
                GP_3_1_FN, FN_IP7_8_6,
-               GP_3_0_FN, FN_IP7_5_3 }
+               GP_3_0_FN, FN_IP7_5_3 ))
        },
-       { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+       { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
                GP_4_31_FN, FN_IP15_5_4,
                GP_4_30_FN, FN_IP15_3_2,
                GP_4_29_FN, FN_IP15_1_0,
@@ -5599,9 +5599,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_4_3_FN, FN_IP9_24_23,
                GP_4_2_FN, FN_IP9_22_21,
                GP_4_1_FN, FN_IP9_20_19,
-               GP_4_0_FN, FN_VI0_CLK }
+               GP_4_0_FN, FN_VI0_CLK ))
        },
-       { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+       { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
                GP_5_31_FN, FN_IP3_24_22,
                GP_5_30_FN, FN_IP13_9_7,
                GP_5_29_FN, FN_IP13_6_5,
@@ -5633,9 +5633,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_5_3_FN, FN_IP11_18_17,
                GP_5_2_FN, FN_IP11_16_15,
                GP_5_1_FN, FN_IP11_14_12,
-               GP_5_0_FN, FN_IP11_11_9 }
+               GP_5_0_FN, FN_IP11_11_9 ))
        },
-       { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+       { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
                GP_6_31_FN, FN_DU0_DOTCLKIN,
                GP_6_30_FN, FN_USB1_OVC,
                GP_6_29_FN, FN_IP14_31_29,
@@ -5667,9 +5667,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_6_3_FN, FN_IP13_13,
                GP_6_2_FN, FN_IP13_12,
                GP_6_1_FN, FN_IP13_11,
-               GP_6_0_FN, FN_IP13_10 }
+               GP_6_0_FN, FN_IP13_10 ))
        },
-       { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+       { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
                0, 0,
                0, 0,
                0, 0,
@@ -5701,11 +5701,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_7_3_FN, FN_IP15_26_24,
                GP_7_2_FN, FN_IP15_23_21,
                GP_7_1_FN, FN_IP15_20_18,
-               GP_7_0_FN, FN_IP15_17_15 }
+               GP_7_0_FN, FN_IP15_17_15 ))
        },
        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
-                            1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
-                            1, 1, 1, 1, 1, 1, 1, 1) {
+                            GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
                /* IP0_31 [1] */
                0, 0,
                /* IP0_30_29 [2] */
@@ -5760,10 +5761,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP0_1 [1] */
                FN_D1, 0,
                /* IP0_0 [1] */
-               FN_D0, 0, }
+               FN_D0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
-                            3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+                            GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
+                            GROUP(
                /* IP1_31_29 [3] */
                FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
                0, 0, 0,
@@ -5796,10 +5798,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
                /* IP1_1_0 [2] */
                FN_A7, FN_MSIOF1_SYNC,
-               0, 0, }
+               0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
-                            2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
+                            GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
+                            GROUP(
                /* IP2_31_30 [2] */
                0, 0, 0, 0,
                /* IP2_29_27 [3] */
@@ -5832,10 +5835,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_A20, FN_SPCLK, 0, 0,
                /* IP2_2_0 [3] */
                FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
-               FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
+               FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
-                            1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
+                            GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
+                            GROUP(
                /* IP3_31 [1] */
                0, 0,
                /* IP3_30_28 [3] */
@@ -5870,10 +5874,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
                /* IP3_2_0 [3] */
                FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
-               0, 0, 0, }
+               0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
-                            1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
+                            GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
+                                  3, 3, 2),
+                            GROUP(
                /* IP4_31 [1] */
                0, 0,
                /* IP4_30_28 [3] */
@@ -5912,10 +5918,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
                0, 0, 0,
                /* IP4_1_0 [2] */
-               FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
+               FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
+               ))
        },
        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
-                            3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
+                            GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
+                            GROUP(
                /* IP5_31_29 [3] */
                FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
                0, 0, 0, 0, 0,
@@ -5950,10 +5958,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP5_2_0 [3] */
                FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
                FN_MSIOF2_TXD_D, FN_VI1_R3_B,
-               0, 0, }
+               0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
-                            2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
+                            GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
+                            GROUP(
                /* IP6_31_30 [2] */
                0, 0, 0, 0,
                /* IP6_29_27 [3] */
@@ -5990,10 +5999,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP6_2_0 [3] */
                FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
                FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
-               0, 0, }
+               0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
-                            2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
+                            GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
+                            GROUP(
                /* IP7_31_30 [2] */
                0, 0, 0, 0,
                /* IP7_29_27 [3] */
@@ -6031,10 +6041,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP7_2_0 [3] */
                FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
                FN_SCIF_CLK_B, FN_GPS_MAG_D,
-               0, 0, }
+               0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
-                            1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
+                            GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
+                            GROUP(
                /* IP8_31 [1] */
                0, 0,
                /* IP8_30_28 [3] */
@@ -6074,10 +6085,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                /* IP8_2_0 [3] */
                FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
-               0, 0, 0, }
+               0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
-                            3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
+                            GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
+                                  1, 1, 3, 3),
+                            GROUP(
                /* IP9_31_29 [3] */
                FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
                FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
@@ -6117,10 +6130,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0,
                /* IP9_2_0 [3] */
                FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
-               0, 0, 0, }
+               0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
-                            3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
+                            GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
+                            GROUP(
                /* IP10_31_29 [3] */
                FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
                0, 0, 0,
@@ -6154,11 +6168,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
                /* IP10_2_0 [3] */
                FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
-               FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
+               FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
-                            2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
-                            3, 3, 3, 3, 3) {
+                            GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
+                                  2, 3, 3, 3, 3, 3),
+                            GROUP(
                /* IP11_31_30 [2] */
                FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
                /* IP11_29_28 [2] */
@@ -6201,10 +6216,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0,
                /* IP11_2_0 [3] */
                FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
-               FN_I2C1_SDA_D, 0, 0, 0, }
+               FN_I2C1_SDA_D, 0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
-                            2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+                            GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
+                            GROUP(
                /* IP12_31_30 [2] */
                0, 0, 0, 0,
                /* IP12_29_27 [3] */
@@ -6242,11 +6258,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP12_3_2 [2] */
                FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
                /* IP12_1_0 [2] */
-               FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
+               FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
-                            1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
-                            3, 2, 2, 3) {
+                            GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
+                                  1, 1, 1, 3, 2, 2, 3),
+                            GROUP(
                /* IP13_31 [1] */
                0, 0,
                /* IP13_30_28 [3] */
@@ -6293,10 +6310,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP13_2_0 [3] */
                FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
                FN_ADICLK_B, FN_MSIOF0_SS1_C,
-               0, 0, 0, }
+               0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
-                            3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
+                            GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
+                                  1, 1, 2),
+                            GROUP(
                /* IP14_31_29 [3] */
                FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
                FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
@@ -6336,10 +6355,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP14_2 [1] */
                FN_SD2_CLK, FN_MMC_CLK,
                /* IP14_1_0 [2] */
-               FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
+               FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
-                            2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
+                            GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
+                            GROUP(
                /* IP15_31_30 [2] */
                0, 0, 0, 0,
                /* IP15_29_27 [3] */
@@ -6377,10 +6397,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP15_3_2 [2] */
                FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
                /* IP15_1_0 [2] */
-               FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
+               FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
-                            4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
+                            GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
+                            GROUP(
                /* IP16_31_28 [4] */
                0, 0, 0, 0, 0, 0, 0, 0,
                0, 0, 0, 0, 0, 0, 0, 0,
@@ -6409,11 +6430,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP16_2_0 [3] */
                FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
                FN_GLO_SDATA_C, FN_VI1_DATA6_C,
-               0, 0, 0, }
+               0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
-                            1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
-                            3, 2, 2, 2, 1, 2, 2, 2) {
+                            GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
+                                  2, 2, 1, 2, 2, 2),
+                            GROUP(
                /* RESERVED [1] */
                0, 0,
                /* SEL_SCIF1 [2] */
@@ -6454,11 +6476,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_TSIF0 [2] */
                FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
                /* SEL_SOF0 [2] */
-               FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+               FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
-                            3, 1, 1, 3, 2, 1, 1, 2, 2,
-                            1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+                            GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
+                                  1, 2, 2, 2, 1, 1, 1),
+                            GROUP(
                /* SEL_SCIF0 [3] */
                FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
                FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
@@ -6502,11 +6525,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* RESERVED [1] */
                0, 0,
                /* SEL_SSI8 [1] */
-               FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+               FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
-                            2, 2, 2, 2, 2, 2, 2, 2,
-                            1, 1, 2, 2, 3, 2, 2, 2, 1) {
+                            GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
+                                  3, 2, 2, 2, 1),
+                            GROUP(
                /* SEL_HSCIF2 [2] */
                FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
                FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
@@ -6544,11 +6568,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* RESERVED [2] */
                0, 0, 0, 0,
                /* RESERVED [1] */
-               0, 0, }
+               0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
-                            3, 2, 2, 1, 1, 1, 1, 3, 2,
-                            2, 3, 1, 1, 1, 2, 2, 2, 2) {
+                            GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
+                                  1, 1, 2, 2, 2, 2),
+                            GROUP(
                /* SEL_SOF1 [3] */
                FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
                FN_SEL_SOF1_4,
@@ -6590,7 +6615,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* RESERVED [2] */
                0, 0, 0, 0,
                /* RESERVED [2] */
-               0, 0, 0, 0, }
+               0, 0, 0, 0, ))
        },
        { },
 };