rockchip: pinctrl: rk3399: add support for the SPI5 controller

[oweals/u-boot.git] / drivers / pinctrl / pinctrl_stm32.c

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 0e74d051c30475d2903a4acbcb7289c0a5a724de..d7b5ea3e1c001b5b840ff46f7a17ce09488b5e3f 100644 (file)
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -7,6 +7,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MAX_PINS_ONE_IP                        70
 #define MODE_BITS_MASK                 3
 #define OSPEED_MASK                    3
 #define PUPD_MASK                      3
@@ -95,7 +96,7 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
                                          struct udevice *periph)
 {
-       u32 pin_mux[50];
+       u32 pin_mux[MAX_PINS_ONE_IP];
        struct fdtdec_phandle_args args;
        int rv, len;
 
@@ -121,11 +122,16 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev,
                if (len < 0)
                        return -EINVAL;
                for (i = 0; i < len; i++) {
+                       struct gpio_desc desc;
                        debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
                        prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
                        prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node);
-
-                       rv = stm32_gpio_config(&gpio_dsc, &gpio_ctl);
+                       rv = uclass_get_device_by_seq(UCLASS_GPIO,
+                                                     gpio_dsc.port, &desc.dev);
+                       if (rv)
+                               return rv;
+                       desc.offset = gpio_dsc.pin;
+                       rv = stm32_gpio_config(&desc, &gpio_ctl);
                        debug("%s: rv = %d\n\n", __func__, rv);
                        if (rv)
                                return rv;