phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets

[oweals/u-boot.git] / drivers / phy / marvell / comphy_a3700.c

diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index a62d672e86f0e13ad3d1444192e876f41089dccd..81f2b636e626f12298164c7ebda85e12bc4e33ba 100644 (file)
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -223,6 +223,17 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
        return ret;
 }
 
+/*
+ * reg_set_indirect
+ *
+ * return: void
+ */
+static void reg_set_indirect(u32 reg, u16 data, u16 mask)
+{
+       reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF);
+       reg_set(rh_vsreg_data, data, mask);
+}
+
 /*
  * comphy_sata_power_up
  *
@@ -230,43 +241,40 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
  */
 static int comphy_sata_power_up(void)
 {
-       int     ret;
+       int ret;
 
        debug_enter();
 
        /*
         * 0. Swap SATA TX lines
         */
-       reg_set(rh_vsreg_addr, vphy_sync_pattern_reg, 0xFFFFFFFF);
-       reg_set(rh_vsreg_data, bs_txd_inv, bs_txd_inv);
+       reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv);
 
        /*
         * 1. Select 40-bit data width width
         */
-       reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
-       reg_set(rh_vsreg_data, 0x800, bs_phyintf_40bit);
+       reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit);
 
        /*
         * 2. Select reference clock and PHY mode (SATA)
         */
-       reg_set(rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF);
        if (get_ref_clk() == 40) {
-               reg_set(rh_vsreg_data, 0x3, 0x00FF); /* 40 MHz */
+               /* 40 MHz */
+               reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF);
        } else {
-               reg_set(rh_vsreg_data, 0x1, 0x00FF); /* 25 MHz */
+               /* 20 MHz */
+               reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF);
        }
 
        /*
         * 3. Use maximum PLL rate (no power save)
         */
-       reg_set(rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF);
-       reg_set(rh_vsreg_data, bs_max_pll_rate, bs_max_pll_rate);
+       reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate);
 
        /*
         * 4. Reset reserved bit (??)
         */
-       reg_set(rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF);
-       reg_set(rh_vsreg_data, 0, bs_phyctrl_frm_pin);
+       reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin);
 
        /*
         * 5. Set vendor-specific configuration (??)