/*
* 1. Enable max PLL.
*/
- reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0);
+ reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
/*
* 2. Select 20 bit SERDES interface.
*/
- reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0);
+ reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
/*
* 3. Force to use reg setting for PCIe mode
*/
- reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0);
+ reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
/*
* 4. Change RX wait
*/
- reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF);
+ reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
/*
* 5. Enable idle sync
*/
- reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0xFFFF);
+ reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
/*
* 6. Enable the output of 100M/125M/500M clock
*/
- reg_set16(MISC_REG0_ADDR(PCIE),
+ reg_set16(phy_addr(PCIE, MISC_REG0),
0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
/*
* 7. Enable TX
*/
- reg_set(PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
+ reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
/*
* 8. Check crystal jumper setting and program the Power and PLL
* Control accordingly
*/
if (get_ref_clk() == 40) {
- reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC63, 0xFFFF); /* 40 MHz */
+ /* 40 MHz */
+ reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
} else {
- reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC62, 0xFFFF); /* 25 MHz */
+ /* 25 MHz */
+ reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
}
/*
* 9. Override Speed_PLL value and use MAC PLL
*/
- reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate,
+ reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
0xFFFF);
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0);
- }
+ if (invert & PHY_POLARITY_TXD_INVERT)
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0);
- }
+ if (invert & PHY_POLARITY_RXD_INVERT)
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
* 11. Release SW reset
*/
- reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE),
+ reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0),
rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
bf_soft_rst | bf_mode_refdiv);
udelay(PLL_SET_DELAY_US);
/* Assert PCLK enabled */
- ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE), /* address */
- rb_txdclk_pclk_en, /* value */
- rb_txdclk_pclk_en, /* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
- POLL_16B_REG); /* 16bit */
+ ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */
+ rb_txdclk_pclk_en, /* value */
+ rb_txdclk_pclk_en, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_16B_REG); /* 16bit */
if (ret == 0)
printf("Failed to lock PCIe PLL\n");
/* 0xd005c300 = 0x1001 */
/* set PRD_TXDEEMPH (3.5db de-emph) */
- reg_set16(LANE_CFG0_ADDR(USB3), 0x1, 0xFF);
+ reg_set16(phy_addr(USB3, LANE_CFG0), 0x1, 0xFF);
/*
* unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
*/
/* unset BIT4: set G2 Tx Datapath with no Delayed Latency */
/* unset BIT6: set Tx Detect Rx Mode at LoZ mode */
- reg_set16(LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF);
+ reg_set16(phy_addr(USB3, LANE_CFG1), 0x0, 0xFFFF);
/* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
- reg_set16(LANE_CFG4_ADDR(USB3), bf_spread_spectrum_clock_en, 0x80);
+ reg_set16(phy_addr(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80);
/*
* set Override Margining Controls From the MAC: Use margining signals
* from lane configuration
*/
- reg_set16(TEST_MODE_CTRL_ADDR(USB3), rb_mode_margin_override, 0xFFFF);
+ reg_set16(phy_addr(USB3, TEST_MODE_CTRL), rb_mode_margin_override,
+ 0xFFFF);
/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
/* set Mode Clock Source = PCLK is generated from REFCLK */
- reg_set16(GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF);
+ reg_set16(phy_addr(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF);
/* set G2 Spread Spectrum Clock Amplitude at 4K */
- reg_set16(GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, 0xF000);
+ reg_set16(phy_addr(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000);
/*
* unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
* Master Current Select
*/
- reg_set16(GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF);
+ reg_set16(phy_addr(USB3, GEN2_SETTINGS_3), 0x0, 0xFFFF);
/*
* 3. Check crystal jumper setting and program the Power and PLL
* Control accordingly
*/
if (get_ref_clk() == 40) {
- reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, 0xFFFF); /* 40 MHz */
+ /* 40 MHz */
+ reg_set16(phy_addr(USB3, PWR_PLL_CTRL), 0xFCA3, 0xFFFF);
} else {
- reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, 0xFFFF); /* 25 MHz */
+ /* 25 MHz */
+ reg_set16(phy_addr(USB3, PWR_PLL_CTRL), 0xFCA2, 0xFFFF);
}
/*
* 4. Change RX wait
*/
- reg_set16(PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF);
+ reg_set16(phy_addr(USB3, PWR_MGM_TIM1), 0x10C, 0xFFFF);
/*
* 5. Enable idle sync
*/
- reg_set16(UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, 0xFFFF);
+ reg_set16(phy_addr(USB3, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
/*
* 6. Enable the output of 500M clock
*/
- reg_set16(MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, 0xFFFF);
+ reg_set16(phy_addr(USB3, MISC_REG0), 0xA00D | rb_clk500m_en, 0xFFFF);
/*
* 7. Set 20-bit data width
*/
- reg_set16(DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF);
+ reg_set16(phy_addr(USB3, DIG_LB_EN), 0x0400, 0xFFFF);
/*
* 8. Override Speed_PLL value and use MAC PLL
*/
- reg_set16(KVCO_CAL_CTRL_ADDR(USB3), 0x0040 | rb_use_max_pll_rate,
+ reg_set16(phy_addr(USB3, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
0xFFFF);
/*
* 9. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(USB3), phy_txd_inv, 0);
- }
+ if (invert & PHY_POLARITY_TXD_INVERT)
+ reg_set16(phy_addr(USB3, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(USB3), phy_rxd_inv, 0);
- }
+ if (invert & PHY_POLARITY_RXD_INVERT)
+ reg_set16(phy_addr(USB3, SYNC_PATTERN), phy_rxd_inv, 0);
/*
* 10. Release SW reset
*/
- reg_set16(GLOB_PHY_CTRL0_ADDR(USB3),
+ reg_set16(phy_addr(USB3, GLOB_PHY_CTRL0),
rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20,
0xFFFF);
udelay(PLL_SET_DELAY_US);
/* Assert PCLK enabled */
- ret = comphy_poll_reg(LANE_STAT1_ADDR(USB3), /* address */
+ ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */
rb_txdclk_pclk_en, /* value */
rb_txdclk_pclk_en, /* mask */
PLL_LOCK_TIMEOUT, /* timeout */
mdelay(10);
/* 9. Program COMPHY register PHY_MODE */
- reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
+ reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
/*
* 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
* source
*/
- reg_set16(sgmiiphy_addr(lane, PHY_MISC_REG0_ADDR), 0, rb_ref_clk_sel);
+ reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel);
/*
* 11. Set correct reference clock frequency in COMPHY register
* REF_FREF_SEL.
*/
if (get_ref_clk() == 40) {
- reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
+ reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
} else {
/* 25MHz */
- reg_set16(sgmiiphy_addr(lane, PHY_PWR_PLL_CTRL_ADDR),
+ reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
}
* bus width
*/
/* 10bit */
- reg_set16(sgmiiphy_addr(lane, PHY_DIG_LB_EN_ADDR), 0,
- rf_data_width_mask);
+ reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask);
/*
* 14. As long as DFE function needs to be enabled in any mode,
* 18. Check the PHY Polarity invert bit
*/
if (invert & PHY_POLARITY_TXD_INVERT)
- reg_set16(sgmiiphy_addr(lane, PHY_SYNC_PATTERN_ADDR),
- phy_txd_inv, 0);
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
if (invert & PHY_POLARITY_RXD_INVERT)
- reg_set16(sgmiiphy_addr(lane, PHY_SYNC_PATTERN_ADDR),
- phy_rxd_inv, 0);
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
/*
* 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
projects / oweals / u-boot.git / blobdiff