// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
#include <asm/arch/clock.h>
#endif
#include "pcie_layerscape_gen4.h"
+#include "pcie_layerscape_fixup_common.h"
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
return -ENOSPC; /* LUT is full */
}
-/* returns the next available streamid for pcie, -errno if failed */
-static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
-{
- int stream_id = pcie->stream_id_cur;
-
- if (stream_id > FSL_PEX_STREAM_ID_END)
- return -EINVAL;
-
- pcie->stream_id_cur++;
-
- return stream_id | ((pcie->idx + 1) << 11);
-}
-
/*
* Program a single LUT entry
*/
bus = bus->parent;
pcie = dev_get_priv(bus);
- streamid = ls_pcie_g4_next_streamid(pcie);
+ streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
if (streamid < 0) {
debug("ERROR: no stream ids free\n");
continue;
+ } else {
+ pcie->stream_id_cur++;
}
index = ls_pcie_g4_next_lut_index(pcie);
}
/* Fixup Kernel DT for PCIe */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
{
struct ls_pcie_g4 *pcie;
}
#else /* !CONFIG_OF_BOARD_SETUP */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
{
}
#endif