clk: imx8mm: add enet clk

[oweals/u-boot.git] / drivers / pci / pcie_layerscape_fixup.c

diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index d504bbda378b636dc93ab38732b2060ff7cfe086..089e031724ab1be0a80e499625505a9814017ea8 100644 (file)
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,8 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -11,8 +11,11 @@
 #include <asm/io.h>
 #include <errno.h>
 #ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
+#include <linux/libfdt.h>
 #include <fdt_support.h>
+#ifdef CONFIG_ARM
+#include <asm/arch/clock.h>
+#endif
 #include "pcie_layerscape.h"
 
 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
@@ -82,7 +85,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
                svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
                if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-                   svr == SVR_LS2048A || svr == SVR_LS2044A)
+                   svr == SVR_LS2048A || svr == SVR_LS2044A ||
+                   svr == SVR_LS2081A || svr == SVR_LS2041A)
                        compat = "fsl,ls2088a-pcie";
                else
                        compat = CONFIG_FSL_PCIE_COMPAT;
@@ -125,19 +129,28 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
        u32 iommu_map[4];
        int nodeoffset;
        int lenp;
+       uint svr;
+       char *compat = NULL;
 
        /* find pci controller node */
        nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
                                                   pcie->dbi_res.start);
        if (nodeoffset < 0) {
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
-               nodeoffset = fdt_node_offset_by_compat_reg(blob,
-                               CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+               svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+               if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+                   svr == SVR_LS2048A || svr == SVR_LS2044A ||
+                   svr == SVR_LS2081A || svr == SVR_LS2041A)
+                       compat = "fsl,ls2088a-pcie";
+               else
+                       compat = CONFIG_FSL_PCIE_COMPAT;
+
+               if (compat)
+                       nodeoffset = fdt_node_offset_by_compat_reg(blob,
+                                               compat, pcie->dbi_res.start);
+#endif
                if (nodeoffset < 0)
                        return;
-#else
-               return;
-#endif
        }
 
        /* get phandle to iommu controller */
@@ -205,7 +218,7 @@ static void fdt_fixup_pcie(void *blob)
 }
 #endif
 
-static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
 {
        int off;
        uint svr;
@@ -217,7 +230,8 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
                svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
                if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-                   svr == SVR_LS2048A || svr == SVR_LS2044A)
+                   svr == SVR_LS2048A || svr == SVR_LS2044A ||
+                   svr == SVR_LS2081A || svr == SVR_LS2041A)
                        compat = "fsl,ls2088a-pcie";
                else
                        compat = CONFIG_FSL_PCIE_COMPAT;
@@ -229,12 +243,33 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
                        return;
        }
 
-       if (pcie->enabled)
+       if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
                fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
        else
                fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 }
 
+static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
+{
+       int off;
+
+       off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
+                                           pcie->dbi_res.start);
+       if (off < 0)
+               return;
+
+       if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
+               fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+       else
+               fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+{
+       ft_pcie_ep_fix(blob, pcie);
+       ft_pcie_rc_fix(blob, pcie);
+}
+
 /* Fixup Kernel DT for PCIe */
 void ft_pci_setup(void *blob, bd_t *bd)
 {