return 0;
}
-int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf,
+int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
uint offset, void **paddress)
{
struct ls_pcie *pcie = dev_get_priv(bus);
return 0;
}
-static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
+static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
{
/* Disable all bars in RC mode */
static void ls_pcie_disable_bars(struct ls_pcie *pcie)
{
- u32 sriov;
-
- sriov = in_le32(pcie->dbi + PCIE_SRIOV);
-
- /*
- * TODO: For PCIe controller with SRIOV, the method to disable bars
- * is different and more complex, so will add later.
- */
- if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
- return;
-
dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
- dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
+ dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
}
static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)