mtd: rawnand: denali: deassert write protect pin

[oweals/u-boot.git] / drivers / pci / pcie_layerscape.c

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 5ad7c287735126d2b65ef8a4508f228de0249f55..39b6d40802500a4b95ec1d3cbd6bf2a75a9ac2df 100644 (file)
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
 
 #include <common.h>
+#include <log.h>
 #include <asm/arch/fsl_serdes.h>
 #include <pci.h>
 #include <asm/io.h>
@@ -243,7 +244,7 @@ static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
        return 0;
 }
 
-int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf,
+int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
                         uint offset, void **paddress)
 {
        struct ls_pcie *pcie = dev_get_priv(bus);
@@ -271,7 +272,7 @@ int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf,
        return 0;
 }
 
-static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
+static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
                               uint offset, ulong *valuep,
                               enum pci_size_t size)
 {
@@ -312,20 +313,9 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
 /* Disable all bars in RC mode */
 static void ls_pcie_disable_bars(struct ls_pcie *pcie)
 {
-       u32 sriov;
-
-       sriov = in_le32(pcie->dbi + PCIE_SRIOV);
-
-       /*
-        * TODO: For PCIe controller with SRIOV, the method to disable bars
-        * is different and more complex, so will add later.
-        */
-       if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
-               return;
-
        dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
        dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
-       dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
+       dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
 }
 
 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
@@ -339,6 +329,7 @@ static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
        dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
 
        ls_pcie_disable_bars(pcie);
+       pcie->stream_id_cur = 0;
 }
 
 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)