+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2014 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
-#include <inttypes.h>
#include <pci.h>
#include <asm/io.h>
-#include <dm/lists.h>
-#include <dm/root.h>
#include <dm/device-internal.h>
+#include <dm/lists.h>
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h>
#endif
/* Since buses may not be numbered yet try a little harder with bus 0 */
if (ret == -ENODEV) {
- ret = uclass_first_device(UCLASS_PCI, busp);
+ ret = uclass_first_device_err(UCLASS_PCI, busp);
if (ret)
return ret;
- else if (!*busp)
- return -ENODEV;
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
}
return ops->write_config(bus, bdf, offset, value, size);
}
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+ u32 clr, u32 set)
+{
+ ulong val;
+ int ret;
+
+ ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
+}
+
int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
enum pci_size_t size)
{
size);
}
-
int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
{
return pci_write_config(bdf, offset, value, PCI_SIZE_32);
return 0;
}
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+ u8 val;
+ int ret;
+
+ ret = dm_pci_read_config8(dev, offset, &val);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return dm_pci_write_config8(dev, offset, val);
+}
+
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+ u16 val;
+ int ret;
+
+ ret = dm_pci_read_config16(dev, offset, &val);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return dm_pci_write_config16(dev, offset, val);
+}
+
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+ u32 val;
+ int ret;
+
+ ret = dm_pci_read_config32(dev, offset, &val);
+ if (ret)
+ return ret;
+ val &= ~clr;
+ val |= set;
+
+ return dm_pci_write_config32(dev, offset, val);
+}
+
static void set_vga_bridge_bits(struct udevice *dev)
{
struct udevice *parent = dev->parent;
return sub_bus;
}
+int pci_generic_mmap_write_config(
+ struct udevice *bus,
+ int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+ pci_dev_t bdf,
+ uint offset,
+ ulong value,
+ enum pci_size_t size)
+{
+ void *address;
+
+ if (addr_f(bus, bdf, offset, &address) < 0)
+ return 0;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(value, address);
+ return 0;
+ case PCI_SIZE_16:
+ writew(value, address);
+ return 0;
+ case PCI_SIZE_32:
+ writel(value, address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+int pci_generic_mmap_read_config(
+ struct udevice *bus,
+ int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+ pci_dev_t bdf,
+ uint offset,
+ ulong *valuep,
+ enum pci_size_t size)
+{
+ void *address;
+
+ if (addr_f(bus, bdf, offset, &address) < 0) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = readb(address);
+ return 0;
+ case PCI_SIZE_16:
+ *valuep = readw(address);
+ return 0;
+ case PCI_SIZE_32:
+ *valuep = readl(address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
int dm_pci_hose_probe_bus(struct udevice *bus)
{
int sub_bus;
* pci_match_one_device - Tell if a PCI device structure has a matching
* PCI device id structure
* @id: single PCI device id structure to match
- * @dev: the PCI device structure to match against
+ * @find: the PCI device id structure to match against
*
- * Returns the matching pci_device_id structure or %NULL if there is no match.
+ * Returns true if the finding pci_device_id structure matched or false if
+ * there is no match.
*/
static bool pci_match_one_id(const struct pci_device_id *id,
const struct pci_device_id *find)
if (ret)
goto error;
debug("%s: Match found: %s\n", __func__, drv->name);
- dev->driver_data = find_id->driver_data;
+ dev->driver_data = id->driver_data;
*devp = dev;
return 0;
}
ret = device_bind_driver(parent, drv, str, devp);
if (ret) {
debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
+ free(str);
return ret;
}
debug("%s: No match found: bound generic driver instead\n", __func__);
found_multi = false;
end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
PCI_MAX_PCI_FUNCTIONS - 1);
- for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
+ for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
bdf += PCI_BDF(0, 0, 1)) {
struct pci_child_platdata *pplat;
struct udevice *dev;
ulong class;
+ if (!PCI_FUNC(bdf))
+ found_multi = false;
if (PCI_FUNC(bdf) && !found_multi)
continue;
/* Check only the first access, we don't expect problems */
return ret;
}
-static int pci_uclass_post_bind(struct udevice *bus)
-{
- /*
- * If there is no pci device listed in the device tree,
- * don't bother scanning the device tree.
- */
- if (bus->of_offset == -1)
- return 0;
-
- /*
- * Scan the device tree for devices. This does not probe the PCI bus,
- * as this is not permitted while binding. It just finds devices
- * mentioned in the device tree.
- *
- * Before relocation, only bind devices marked for pre-relocation
- * use.
- */
- return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
- gd->flags & GD_FLG_RELOC ? false : true);
-}
-
-static int decode_regions(struct pci_controller *hose, const void *blob,
- int parent_node, int node)
+static void decode_regions(struct pci_controller *hose, ofnode parent_node,
+ ofnode node)
{
int pci_addr_cells, addr_cells, size_cells;
- phys_addr_t base = 0, size;
int cells_per_record;
const u32 *prop;
int len;
int i;
- prop = fdt_getprop(blob, node, "ranges", &len);
- if (!prop)
- return -EINVAL;
- pci_addr_cells = fdt_address_cells(blob, node);
- addr_cells = fdt_address_cells(blob, parent_node);
- size_cells = fdt_size_cells(blob, node);
+ prop = ofnode_get_property(node, "ranges", &len);
+ if (!prop) {
+ debug("%s: Cannot decode regions\n", __func__);
+ return;
+ }
+
+ pci_addr_cells = ofnode_read_simple_addr_cells(node);
+ addr_cells = ofnode_read_simple_addr_cells(parent_node);
+ size_cells = ofnode_read_simple_size_cells(node);
/* PCI addresses are always 3-cells */
len /= sizeof(u32);
prop += addr_cells;
size = fdtdec_get_number(prop, size_cells);
prop += size_cells;
- debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
- ", size=%" PRIx64 ", space_code=%d\n", __func__,
- hose->region_count, pci_addr, addr, size, space_code);
+ debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
+ __func__, hose->region_count, pci_addr, addr, size, space_code);
if (space_code & 2) {
type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
PCI_REGION_MEM;
} else {
continue;
}
+
+ if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+ type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
+ debug(" - beyond the 32-bit boundary, ignoring\n");
+ continue;
+ }
+
pos = -1;
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == type)
}
/* Add a region for our local memory */
+#ifdef CONFIG_NR_DRAM_BANKS
+ bd_t *bd = gd->bd;
+
+ if (!bd)
+ return;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ pci_set_region(hose->regions + hose->region_count++,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ }
+ }
+#else
+ phys_addr_t base = 0, size;
+
size = gd->ram_size;
#ifdef CONFIG_SYS_SDRAM_BASE
base = CONFIG_SYS_SDRAM_BASE;
#endif
if (gd->pci_ram_top && gd->pci_ram_top < base + size)
size = gd->pci_ram_top - base;
- pci_set_region(hose->regions + hose->region_count++, base, base,
- size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ if (size)
+ pci_set_region(hose->regions + hose->region_count++, base,
+ base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+#endif
- return 0;
+ return;
}
static int pci_uclass_pre_probe(struct udevice *bus)
{
struct pci_controller *hose;
- int ret;
debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
bus->parent->name);
hose = bus->uclass_priv;
/* For bridges, use the top-level PCI controller */
- if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
+ if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus;
- ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
- bus->of_offset);
- if (ret) {
- debug("%s: Cannot decode regions\n", __func__);
- return ret;
- }
+ decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
} else {
struct pci_controller *parent_hose;
struct fdt_pci_addr addr;
int ret;
- if (dev->of_offset == -1)
+ if (!dev_of_valid(dev))
return 0;
- /*
- * We could read vendor, device, class if available. But for now we
- * just check the address.
- */
pplat = dev_get_parent_platdata(dev);
- ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
- FDT_PCI_SPACE_CONFIG, "reg", &addr);
+ /* Extract vendor id and device id if available */
+ ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
+
+ /* Extract the devfn from fdt_pci_addr */
+ ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
+ &addr);
if (ret) {
if (ret != -ENOENT)
return -EINVAL;
} else {
- /* extract the devfn from fdt_pci_addr */
pplat->devfn = addr.phys_hi & 0xff00;
}
struct pci_region *res;
int i;
+ if (hose->region_count == 0) {
+ *pa = bus_addr;
+ return 0;
+ }
+
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
ctlr = pci_get_controller(dev);
hose = dev_get_uclass_priv(ctlr);
+ if (hose->region_count == 0) {
+ *ba = phys_addr;
+ return 0;
+ }
+
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
}
+int dm_pci_find_capability(struct udevice *dev, int cap)
+{
+ u16 status;
+ u8 header_type;
+ int ttl = PCI_FIND_CAP_TTL;
+ u8 id;
+ u16 ent;
+ u8 pos;
+
+ dm_pci_read_config16(dev, PCI_STATUS, &status);
+ if (!(status & PCI_STATUS_CAP_LIST))
+ return 0;
+
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
+ pos = PCI_CB_CAPABILITY_LIST;
+ else
+ pos = PCI_CAPABILITY_LIST;
+
+ dm_pci_read_config8(dev, pos, &pos);
+ while (ttl--) {
+ if (pos < PCI_STD_HEADER_SIZEOF)
+ break;
+ pos &= ~3;
+ dm_pci_read_config16(dev, pos, &ent);
+
+ id = ent & 0xff;
+ if (id == 0xff)
+ break;
+ if (id == cap)
+ return pos;
+ pos = (ent >> 8);
+ }
+
+ return 0;
+}
+
+int dm_pci_find_ext_capability(struct udevice *dev, int cap)
+{
+ u32 header;
+ int ttl;
+ int pos = PCI_CFG_SPACE_SIZE;
+
+ /* minimum 8 bytes per capability */
+ ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+ dm_pci_read_config32(dev, pos, &header);
+ /*
+ * If we have no capabilities, this is indicated by cap ID,
+ * cap version and next pointer all being 0.
+ */
+ if (header == 0)
+ return 0;
+
+ while (ttl--) {
+ if (PCI_EXT_CAP_ID(header) == cap)
+ return pos;
+
+ pos = PCI_EXT_CAP_NEXT(header);
+ if (pos < PCI_CFG_SPACE_SIZE)
+ break;
+
+ dm_pci_read_config32(dev, pos, &header);
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .post_bind = pci_uclass_post_bind,
+ .post_bind = dm_scan_fdt_dev,
.pre_probe = pci_uclass_pre_probe,
.post_probe = pci_uclass_post_probe,
.child_post_bind = pci_uclass_child_post_bind,
projects / oweals / u-boot.git / blobdiff