dm: core: Move "/clock" node scan into function

[oweals/u-boot.git] / drivers / pci / pci-uclass.c

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 5eb68415cd7c3dbdfc7e021d742d1a78feaab9f3..eb118f3496ef5f90e3193b3dbc90b482edc6bb9a 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -7,7 +7,6 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <inttypes.h>
 #include <pci.h>
 #include <asm/io.h>
 #include <dm/device-internal.h>
@@ -854,9 +853,8 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
                prop += addr_cells;
                size = fdtdec_get_number(prop, size_cells);
                prop += size_cells;
-               debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
-                     ", size=%" PRIx64 ", space_code=%d\n", __func__,
-                     hose->region_count, pci_addr, addr, size, space_code);
+               debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
+                     __func__, hose->region_count, pci_addr, addr, size, space_code);
                if (space_code & 2) {
                        type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
                                        PCI_REGION_MEM;
@@ -1320,6 +1318,74 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
        return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 }
 
+int dm_pci_find_capability(struct udevice *dev, int cap)
+{
+       u16 status;
+       u8 header_type;
+       int ttl = PCI_FIND_CAP_TTL;
+       u8 id;
+       u16 ent;
+       u8 pos;
+
+       dm_pci_read_config16(dev, PCI_STATUS, &status);
+       if (!(status & PCI_STATUS_CAP_LIST))
+               return 0;
+
+       dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+       if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
+               pos = PCI_CB_CAPABILITY_LIST;
+       else
+               pos = PCI_CAPABILITY_LIST;
+
+       dm_pci_read_config8(dev, pos, &pos);
+       while (ttl--) {
+               if (pos < PCI_STD_HEADER_SIZEOF)
+                       break;
+               pos &= ~3;
+               dm_pci_read_config16(dev, pos, &ent);
+
+               id = ent & 0xff;
+               if (id == 0xff)
+                       break;
+               if (id == cap)
+                       return pos;
+               pos = (ent >> 8);
+       }
+
+       return 0;
+}
+
+int dm_pci_find_ext_capability(struct udevice *dev, int cap)
+{
+       u32 header;
+       int ttl;
+       int pos = PCI_CFG_SPACE_SIZE;
+
+       /* minimum 8 bytes per capability */
+       ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+       dm_pci_read_config32(dev, pos, &header);
+       /*
+        * If we have no capabilities, this is indicated by cap ID,
+        * cap version and next pointer all being 0.
+        */
+       if (header == 0)
+               return 0;
+
+       while (ttl--) {
+               if (PCI_EXT_CAP_ID(header) == cap)
+                       return pos;
+
+               pos = PCI_EXT_CAP_NEXT(header);
+               if (pos < PCI_CFG_SPACE_SIZE)
+                       break;
+
+               dm_pci_read_config32(dev, pos, &header);
+       }
+
+       return 0;
+}
+
 UCLASS_DRIVER(pci) = {
        .id             = UCLASS_PCI,
        .name           = "pci",