SPEAr : smi driver support for SPEAr SoCs

[oweals/u-boot.git] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index ee89aaae5af766336e5701aa269e387b16b9d420..fe57926d7ea66bb8250c4e5942c2379f19e26c0b 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -42,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FSL_PCI_PBFR           0x44
 #define FSL_PCIE_CAP_ID                0x4c
 #define FSL_PCIE_CFG_RDY       0x4b0
+#define FSL_PROG_IF_AGENT      0x1
 
 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
                                pci_dev_t dev, int sub_bus);
@@ -85,6 +86,15 @@ static void set_inbound_window(volatile pit_t *pi,
        out_be32(&pi->piwar, flag | sz);
 }
 
+int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
+{
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
+
+       pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+
+       return fsl_is_pci_agent(hose);
+}
+
 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
                                         u64 out_lo, u8 pcie_cap,
                                         volatile pit_t *pi)
@@ -412,6 +422,65 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
        }
 }
 
+int fsl_is_pci_agent(struct pci_controller *hose)
+{
+       u8 prog_if;
+       pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+
+       pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
+
+       return (prog_if == FSL_PROG_IF_AGENT);
+}
+
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+                       struct pci_controller *hose, int busno)
+{
+       volatile ccsr_fsl_pci_t *pci;
+       struct pci_region *r;
+
+       pci = (ccsr_fsl_pci_t *) pci_info->regs;
+
+       /* on non-PCIe controllers we don't have pme_msg_det so this code
+        * should do nothing since the read will return 0
+        */
+       if (in_be32(&pci->pme_msg_det)) {
+               out_be32(&pci->pme_msg_det, 0xffffffff);
+               debug (" with errors.  Clearing.  Now 0x%08x",
+                       pci->pme_msg_det);
+       }
+
+       r = hose->regions + hose->region_count;
+
+       /* outbound memory */
+       pci_set_region(r++,
+                       pci_info->mem_bus,
+                       pci_info->mem_phys,
+                       pci_info->mem_size,
+                       PCI_REGION_MEM);
+
+       /* outbound io */
+       pci_set_region(r++,
+                       pci_info->io_bus,
+                       pci_info->io_phys,
+                       pci_info->io_size,
+                       PCI_REGION_IO);
+
+       hose->region_count = r - hose->regions;
+       hose->first_busno = busno;
+
+       fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+
+       if (fsl_is_pci_agent(hose)) {
+               fsl_pci_config_unlock(hose);
+               hose->last_busno = hose->first_busno;
+       }
+
+       printf("    PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
+                       hose->first_busno, hose->last_busno);
+
+       return(hose->last_busno + 1);
+}
+
 /* Enable inbound PCI config cycles for agent/endpoint interface */
 void fsl_pci_config_unlock(struct pci_controller *hose)
 {