Merge git://git.denx.de/u-boot-fsl-qoriq

[oweals/u-boot.git] / drivers / pci / Kconfig

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b8376b4f47bf315b542d9e050a3cffb45d8f4dd0..58f128d8a62c5a1e18101d01fc5ea3bb2ed241fe 100644 (file)
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -1,6 +1,6 @@
 menuconfig PCI
        bool "PCI support"
-       default y if PPC || X86
+       default y if PPC
        help
          Enable support for PCI (Peripheral Interconnect Bus), a type of bus
          used on some devices to allow the CPU to communicate with its
@@ -9,7 +9,7 @@ menuconfig PCI
 if PCI
 
 config DM_PCI
-       bool "Enable driver mode for PCI"
+       bool "Enable driver model for PCI"
        depends on DM
        help
          Use driver model for PCI. Driver model is the new method for
@@ -33,6 +33,23 @@ config PCI_PNP
        help
          Enable PCI memory and I/O space resource allocation and assignment.
 
+config PCIE_ECAM_GENERIC
+       bool "Generic ECAM-based PCI host controller support"
+       default n
+       depends on DM_PCI
+       help
+         Say Y here if you want to enable support for generic ECAM-based
+         PCIe host controllers, such as the one emulated by QEMU.
+
+config PCIE_DW_MVEBU
+       bool "Enable Armada-8K PCIe driver (DesignWare core)"
+       depends on DM_PCI
+       depends on ARMADA_8K
+       help
+         Say Y here if you want to enable PCIe controller support on
+         Armada-8K SoCs. The PCIe controller on Armada-8K is based on
+         DesignWare hardware.
+
 config PCI_SANDBOX
        bool "Sandbox PCI support"
        depends on SANDBOX && DM_PCI
@@ -61,4 +78,12 @@ config PCI_XILINX
          Enable support for the Xilinx AXI bridge for PCI express, an IP block
          which can be used on some generations of Xilinx FPGAs.
 
+config PCIE_LAYERSCAPE
+       bool "Layerscape PCIe support"
+       depends on DM_PCI
+       help
+         Support Layerscape PCIe. The Layerscape SoC may have one or several
+         PCIe controllers. The PCIe may works in RC or EP mode according to
+         RCW[HOST_AGT_PEX] setting.
+
 endif