driver: net: fsl-mc: Update print to reflect correct string

[oweals/u-boot.git] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 5f0f2005ceb3cc42621252968c994a9a74256cc1..b3821c31a91dc36f0cf6e7169c9ecc7bbad10c02 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <phy.h>
 #include <miiphy.h>
+#include <wait_bit.h>
 #include <watchdog.h>
 #include <asm/system.h>
 #include <asm/arch/hardware.h>
@@ -27,10 +28,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if !defined(CONFIG_PHYLIB)
-# error XILINX_GEM_ETHERNET requires PHYLIB
-#endif
-
 /* Bit/mask specification */
 #define ZYNQ_GEM_PHYMNTNC_OP_MASK      0x40020000 /* operation mask bits */
 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK    0x20000000 /* read operation */
@@ -60,7 +57,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_GEM_NWCFG_SPEED1000       0x000000400 /* 1Gbps operation */
 #define ZYNQ_GEM_NWCFG_FDEN            0x000000002 /* Full Duplex mode */
 #define ZYNQ_GEM_NWCFG_FSREM           0x000020000 /* FCS removal */
+#ifdef CONFIG_ARM64
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x000100000 /* Div pclk by 64, max 160MHz */
+#else
 #define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x0000c0000 /* Div pclk by 48, max 120MHz */
+#endif
 
 #ifdef CONFIG_ARM64
 # define ZYNQ_GEM_DBUS_WIDTH   (1 << 21) /* 64 bit bus */
@@ -452,38 +453,6 @@ static int zynq_gem_init(struct udevice *dev)
        return 0;
 }
 
-static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
-                       bool set, unsigned int timeout)
-{
-       u32 val;
-       unsigned long start = get_timer(0);
-
-       while (1) {
-               val = readl(reg);
-
-               if (!set)
-                       val = ~val;
-
-               if ((val & mask) == mask)
-                       return 0;
-
-               if (get_timer(start) > timeout)
-                       break;
-
-               if (ctrlc()) {
-                       puts("Abort\n");
-                       return -EINTR;
-               }
-
-               udelay(1);
-       }
-
-       debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
-             func, reg, mask, set);
-
-       return -ETIMEDOUT;
-}
-
 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 {
        u32 addr, size;
@@ -525,50 +494,61 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
                printf("TX buffers exhausted in mid frame\n");
 
        return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
-                           true, 20000);
+                           true, 20000, true);
 }
 
 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
 {
        int frame_len;
+       u32 addr;
        struct zynq_gem_priv *priv = dev_get_priv(dev);
        struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
-       struct emac_bd *first_bd;
 
        if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
-               return 0;
+               return -1;
 
        if (!(current_bd->status &
                        (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
                printf("GEM: SOF or EOF not set for last buffer received!\n");
-               return 0;
+               return -1;
        }
 
        frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
-       if (frame_len) {
-               u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
-               addr &= ~(ARCH_DMA_MINALIGN - 1);
+       if (!frame_len) {
+               printf("%s: Zero size packet?\n", __func__);
+               return -1;
+       }
 
-               net_process_received_packet((u8 *)(ulong)addr, frame_len);
+       addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
+       addr &= ~(ARCH_DMA_MINALIGN - 1);
+       *packetp = (uchar *)(uintptr_t)addr;
 
-               if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
-                       priv->rx_first_buf = priv->rxbd_current;
-               else {
-                       current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
-                       current_bd->status = 0xF0000000; /* FIXME */
-               }
+       return frame_len;
+}
 
-               if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
-                       first_bd = &priv->rx_bd[priv->rx_first_buf];
-                       first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
-                       first_bd->status = 0xF0000000;
-               }
+static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+       struct zynq_gem_priv *priv = dev_get_priv(dev);
+       struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
+       struct emac_bd *first_bd;
+
+       if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
+               priv->rx_first_buf = priv->rxbd_current;
+       } else {
+               current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+               current_bd->status = 0xF0000000; /* FIXME */
+       }
 
-               if ((++priv->rxbd_current) >= RX_BUF)
-                       priv->rxbd_current = 0;
+       if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
+               first_bd = &priv->rx_bd[priv->rx_first_buf];
+               first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+               first_bd->status = 0xF0000000;
        }
 
+       if ((++priv->rxbd_current) >= RX_BUF)
+               priv->rxbd_current = 0;
+
        return 0;
 }
 
@@ -651,6 +631,7 @@ static const struct eth_ops zynq_gem_ops = {
        .start                  = zynq_gem_init,
        .send                   = zynq_gem_send,
        .recv                   = zynq_gem_recv,
+       .free_pkt               = zynq_gem_free_pkt,
        .stop                   = zynq_gem_halt,
        .write_hwaddr           = zynq_gem_setup_mac,
 };