Revert "ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes"

[oweals/u-boot.git] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 52a8f2760012f87f3582f4878b502fce2711d789..3319e10467d0a36c29e0d962428bf01a542c6684 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -24,7 +24,7 @@
 #include <asm/system.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -53,16 +53,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_GEM_NWCTRL_MDEN_MASK      0x00000010 /* Enable MDIO port */
 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK   0x00000200 /* Start tx (tx_go) */
 
-#define ZYNQ_GEM_NWCFG_SPEED100                0x000000001 /* 100 Mbps operation */
-#define ZYNQ_GEM_NWCFG_SPEED1000       0x000000400 /* 1Gbps operation */
-#define ZYNQ_GEM_NWCFG_FDEN            0x000000002 /* Full Duplex mode */
-#define ZYNQ_GEM_NWCFG_FSREM           0x000020000 /* FCS removal */
-#define ZYNQ_GEM_NWCFG_SGMII_ENBL      0x080000000 /* SGMII Enable */
-#define ZYNQ_GEM_NWCFG_PCS_SEL         0x000000800 /* PCS select */
+#define ZYNQ_GEM_NWCFG_SPEED100                0x00000001 /* 100 Mbps operation */
+#define ZYNQ_GEM_NWCFG_SPEED1000       0x00000400 /* 1Gbps operation */
+#define ZYNQ_GEM_NWCFG_FDEN            0x00000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_FSREM           0x00020000 /* FCS removal */
+#define ZYNQ_GEM_NWCFG_SGMII_ENBL      0x08000000 /* SGMII Enable */
+#define ZYNQ_GEM_NWCFG_PCS_SEL         0x00000800 /* PCS select */
 #ifdef CONFIG_ARM64
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x000100000 /* Div pclk by 64, max 160MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x00100000 /* Div pclk by 64, max 160MHz */
 #else
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x0000c0000 /* Div pclk by 48, max 120MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x000c0000 /* Div pclk by 48, max 120MHz */
 #endif
 
 #ifdef CONFIG_ARM64
@@ -93,6 +93,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ZYNQ_GEM_TSR_DONE              0x00000020 /* Tx done mask */
 
+#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL     0x1000
+
 /* Use MII register 1 (MII status register) to detect PHY */
 #define PHY_DETECT_REG  1
 
@@ -139,7 +141,9 @@ struct zynq_gem_regs {
        u32 reserved6[18];
 #define STAT_SIZE      44
        u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
-       u32 reserved7[164];
+       u32 reserved9[20];
+       u32 pcscntrl;
+       u32 reserved7[143];
        u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
        u32 reserved8[15];
        u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
@@ -175,6 +179,7 @@ struct zynq_gem_priv {
        struct zynq_gem_regs *iobase;
        phy_interface_t interface;
        struct phy_device *phydev;
+       int phy_of_handle;
        struct mii_dev *bus;
 };
 
@@ -348,14 +353,17 @@ static int zynq_phy_init(struct udevice *dev)
        priv->phydev->supported = supported | ADVERTISED_Pause |
                                  ADVERTISED_Asym_Pause;
        priv->phydev->advertising = priv->phydev->supported;
-       phy_config(priv->phydev);
 
-       return 0;
+       if (priv->phy_of_handle > 0)
+               priv->phydev->dev->of_offset = priv->phy_of_handle;
+
+       return phy_config(priv->phydev);
 }
 
 static int zynq_gem_init(struct udevice *dev)
 {
        u32 i, nwconfig;
+       int ret;
        unsigned long clk_rate = 0;
        struct zynq_gem_priv *priv = dev_get_priv(dev);
        struct zynq_gem_regs *regs = priv->iobase;
@@ -423,7 +431,9 @@ static int zynq_gem_init(struct udevice *dev)
                priv->init++;
        }
 
-       phy_startup(priv->phydev);
+       ret = phy_startup(priv->phydev);
+       if (ret)
+               return ret;
 
        if (!priv->phydev->link) {
                printf("%s: No link.\n", priv->phydev->dev->name);
@@ -432,9 +442,14 @@ static int zynq_gem_init(struct udevice *dev)
 
        nwconfig = ZYNQ_GEM_NWCFG_INIT;
 
-       if (priv->interface == PHY_INTERFACE_MODE_SGMII)
+       if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
                nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
                            ZYNQ_GEM_NWCFG_PCS_SEL;
+#ifdef CONFIG_ARM64
+               writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+                      &regs->pcscntrl);
+#endif
+       }
 
        switch (priv->phydev->speed) {
        case SPEED_1000:
@@ -666,7 +681,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 {
        struct eth_pdata *pdata = dev_get_platdata(dev);
        struct zynq_gem_priv *priv = dev_get_priv(dev);
-       int offset = 0;
        const char *phy_mode;
 
        pdata->iobase = (phys_addr_t)dev_get_addr(dev);
@@ -675,10 +689,11 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
        priv->emio = 0;
        priv->phyaddr = -1;
 
-       offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
-                                      "phy-handle");
-       if (offset > 0)
-               priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+       priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
+                                       dev->of_offset, "phy-handle");
+       if (priv->phy_of_handle > 0)
+               priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
+                                       priv->phy_of_handle, "reg", -1);
 
        phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
        if (phy_mode)