* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
static void adjust_link(struct eth_device *dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
&& !defined(BITBANGMII)
-static int tsec_miiphy_write(char *devname, unsigned char addr,
+static int tsec_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
-static int tsec_miiphy_read(char *devname, unsigned char addr,
+static int tsec_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
#endif
#ifdef CONFIG_MCAST_TFTP
#endif
};
+/*
+ * Initialize all the TSEC devices
+ *
+ * Returns the number of TSEC devices that were initialized
+ */
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
{
int i;
+ int ret, count = 0;
- for (i = 0; i < num; i++)
- tsec_initialize(bis, &tsecs[i]);
+ for (i = 0; i < num; i++) {
+ ret = tsec_initialize(bis, &tsecs[i]);
+ if (ret > 0)
+ count += ret;
+ }
- return 0;
+ return count;
}
int tsec_standard_init(bd_t *bis)
| TBIANA_FULL_DUPLEX \
)
-/* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
-#define TBICR_SETTINGS ( \
+/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
+#ifndef CONFIG_TSEC_TBICR_SETTINGS
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
+#endif /* CONFIG_TSEC_TBICR_SETTINGS */
/* Configure the TBI for SGMII operation */
static void tsec_configure_serdes(struct tsec_private *priv)
tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
TBICON_CLK_SELECT);
tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
- TBICR_SETTINGS);
+ CONFIG_TSEC_TBICR_SETTINGS);
}
/* Discover which PHY is attached to the device, and configure it
* (ie - we're capable and it's not done)
*/
mii_reg = read_phy_reg(priv, MIIM_STATUS);
- if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
int i = 0;
puts("Waiting for PHY auto negotiation to complete");
- while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
static uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
{
/* We're using autonegotiation */
- if (mii_reg & PHY_BMSR_AUTN_ABLE) {
+ if (mii_reg & BMSR_ANEGCAPABLE) {
uint lpa = 0;
uint gblpa = 0;
/* Check for gigabit capability */
- if (mii_reg & PHY_BMSR_EXT) {
+ if (mii_reg & BMSR_ERCAP) {
/* We want a list of states supported by
* both PHYs in the link
*/
- gblpa = read_phy_reg(priv, PHY_1000BTSR);
- gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
+ gblpa = read_phy_reg(priv, MII_STAT1000);
+ gblpa &= read_phy_reg(priv, MII_CTRL1000) << 2;
}
/* Set the baseline so we only have to set them
return 0;
}
- lpa = read_phy_reg(priv, PHY_ANAR);
- lpa &= read_phy_reg(priv, PHY_ANLPAR);
+ lpa = read_phy_reg(priv, MII_ADVERTISE);
+ lpa &= read_phy_reg(priv, MII_LPA);
- if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
+ if (lpa & (LPA_100FULL | LPA_100HALF)) {
priv->speed = 100;
- if (lpa & PHY_ANLPAR_TXFD)
+ if (lpa & LPA_100FULL)
priv->duplexity = 1;
- } else if (lpa & PHY_ANLPAR_10FD)
+ } else if (lpa & LPA_10FULL)
priv->duplexity = 1;
} else {
- uint bmcr = read_phy_reg(priv, PHY_BMCR);
+ uint bmcr = read_phy_reg(priv, MII_BMCR);
priv->speed = 10;
priv->duplexity = 0;
- if (bmcr & PHY_BMCR_DPLX)
+ if (bmcr & BMCR_FULLDPLX)
priv->duplexity = 1;
- if (bmcr & PHY_BMCR_1000_MBPS)
+ if (bmcr & BMCR_SPEED1000)
priv->speed = 1000;
- else if (bmcr & PHY_BMCR_100_MBPS)
+ else if (bmcr & BMCR_SPEED100)
priv->speed = 100;
}
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
- while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
+ while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))
+ != (IEVENT_GRSC | IEVENT_GTSC)) ;
regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
},
};
+/* micrel KSZ804 */
+static struct phy_info phy_info_ksz804 = {
+ 0x0022151,
+ "Micrel KSZ804 PHY",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ {MII_BMCR, BMCR_RESET, NULL},
+ {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ {MII_BMSR, miim_read, NULL},
+ {MII_BMSR, miim_read, &mii_parse_sr},
+ {MII_BMSR, miim_read, &mii_parse_link},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ }
+};
+
/* a generic flavor. */
static struct phy_info phy_info_generic = {
0,
"Unknown/Generic PHY",
32,
(struct phy_cmd[]) { /* config */
- {PHY_BMCR, PHY_BMCR_RESET, NULL},
- {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
+ {MII_BMCR, BMCR_RESET, NULL},
+ {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
- {PHY_BMSR, miim_read, NULL},
- {PHY_BMSR, miim_read, &mii_parse_sr},
- {PHY_BMSR, miim_read, &mii_parse_link},
+ {MII_BMSR, miim_read, NULL},
+ {MII_BMSR, miim_read, &mii_parse_sr},
+ {MII_BMSR, miim_read, &mii_parse_link},
{miim_end,}
},
(struct phy_cmd[]) { /* shutdown */
&phy_info_M88E1145,
&phy_info_M88E1149S,
&phy_info_dm9161,
+ &phy_info_ksz804,
&phy_info_lxt971,
&phy_info_VSC8211,
&phy_info_VSC8244,
* Returns:
* 0 on success
*/
-static int tsec_miiphy_read(char *devname, unsigned char addr,
+static int tsec_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
unsigned short ret;
* Returns:
* 0 on success
*/
-static int tsec_miiphy_write(char *devname, unsigned char addr,
+static int tsec_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
struct tsec_private *priv = privlist[0];