CONFIG_DRIVER_SMC911X_16_BIT shall be set"
#endif
-#ifdef CONFIG_DRIVER_SMC911X_32_BIT
+#if defined (CONFIG_DRIVER_SMC911X_32_BIT)
static inline u32 reg_read(u32 addr)
{
return *(volatile u32*)addr;
{
*(volatile u32*)addr = val;
}
-#elif CONFIG_DRIVER_SMC911X_16_BIT
+#elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
static inline u32 reg_read(u32 addr)
{
volatile u16 *addr_16 = (u16 *)addr;
#error "SMC911X: undefined bus width"
#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
+u32 pkt_data_pull(u32 addr) \
+ __attribute__ ((weak, alias ("reg_read")));
+void pkt_data_push(u32 addr, u32 val) \
+ __attribute__ ((weak, alias ("reg_write")));
+
#define mdelay(n) udelay((n)*1000)
/* Below are the register offsets and bit definitions
val = reg_read(BYTE_TEST);
if (val != 0x87654321) {
- printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val);
+ printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
goto err_out;
}
if (chip_ids[i].id == val) break;
}
if (!chip_ids[i].id) {
- printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
+ printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
goto err_out;
}
tmplen = (length + 3) / 4;
while (tmplen--)
- reg_write(TX_DATA_FIFO, *data++);
+ pkt_data_push(TX_DATA_FIFO, *data++);
/* wait for transmission */
while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
tmplen = (pktlen + 2+ 3) / 4;
while (tmplen--)
- *data++ = reg_read(RX_DATA_FIFO);
+ *data++ = pkt_data_pull(RX_DATA_FIFO);
if (status & RX_STS_ES)
printf(DRIVERNAME