*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
+#include <asm/gpio.h>
/* Registers */
#define RAVB_REG_CCC 0x000
struct phy_device *phydev;
struct mii_dev *bus;
void __iomem *iobase;
+ struct clk clk;
+ struct gpio_desc reset_gpio;
};
static inline void ravb_flush_dcache(u32 addr, u32 len)
struct phy_device *phydev;
int mask = 0xffffffff, reg;
+ if (dm_gpio_is_valid(ð->reset_gpio)) {
+ dm_gpio_set_value(ð->reset_gpio, 1);
+ mdelay(20);
+ dm_gpio_set_value(ð->reset_gpio, 0);
+ mdelay(1);
+ }
+
phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
if (!phydev)
return -ENODEV;
struct ravb_priv *eth = dev_get_priv(dev);
int ret;
- ret = ravb_reset(dev);
+ ret = clk_enable(ð->clk);
if (ret)
return ret;
+ ret = ravb_reset(dev);
+ if (ret)
+ goto err;
+
ravb_base_desc_init(eth);
ravb_tx_desc_init(eth);
ravb_rx_desc_init(eth);
ret = ravb_config(dev);
if (ret)
- return ret;
+ goto err;
/* Setting the control will start the AVB-DMAC process. */
writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
return 0;
+
+err:
+ clk_disable(ð->clk);
+ return ret;
}
static void ravb_stop(struct udevice *dev)
{
+ struct ravb_priv *eth = dev_get_priv(dev);
+
ravb_reset(dev);
+ clk_disable(ð->clk);
}
static int ravb_probe(struct udevice *dev)
iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
eth->iobase = iobase;
+ ret = clk_get_by_index(dev, 0, ð->clk);
+ if (ret < 0)
+ goto err_mdio_alloc;
+
+ gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
+ ð->reset_gpio, GPIOD_IS_OUT);
+
mdiodev = mdio_alloc();
if (!mdiodev) {
ret = -ENOMEM;
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
+ dm_gpio_free(dev, ð->reset_gpio);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;