net: Add MSCC ServalT network driver.

[oweals/u-boot.git] / drivers / net / pic32_mdio.c

diff --git a/drivers/net/pic32_mdio.c b/drivers/net/pic32_mdio.c
index 578fc969051e1e51e6aa96344dc24b31d565df2f..1aa5b1d8dac7061ca2ef03c32895b6e34b7c534b 100644 (file)
--- a/drivers/net/pic32_mdio.c
+++ b/drivers/net/pic32_mdio.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * pic32_mdio.c: PIC32 MDIO/MII driver, part of pic32_eth.c.
  *
  * Copyright 2015 Microchip Inc.
  *     Purna Chandra Mandal <purna.mandal@microchip.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <phy.h>
@@ -22,8 +21,8 @@ static int pic32_mdio_write(struct mii_dev *bus,
        struct pic32_mii_regs *mii_regs = bus->priv;
 
        /* Wait for the previous operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        /* Put phyaddr and regaddr into MIIMADD */
        v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
@@ -36,8 +35,8 @@ static int pic32_mdio_write(struct mii_dev *bus,
        udelay(12);
 
        /* Wait for write to complete */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        return 0;
 }
@@ -48,8 +47,8 @@ static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
        struct pic32_mii_regs *mii_regs = bus->priv;
 
        /* Wait for the previous operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        /* Put phyaddr and regaddr into MIIMADD */
        v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
@@ -62,9 +61,9 @@ static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
        udelay(12);
 
        /* Wait for read to complete */
-       wait_for_bit(__func__, &mii_regs->mind.raw,
-                    MIIMIND_NOTVALID | MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&mii_regs->mind.raw,
+                         MIIMIND_NOTVALID | MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, false);
 
        /* Clear the command register */
        writel(0, &mii_regs->mcmd.raw);
@@ -82,22 +81,22 @@ static int pic32_mdio_reset(struct mii_dev *bus)
        writel(MIIMCFG_RSTMGMT, &mii_regs->mcfg.raw);
 
        /* Wait for the operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
                     false, CONFIG_SYS_HZ, true);
 
        /* Clear reset bit */
        writel(0, &mii_regs->mcfg);
 
        /* Wait for the operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        /* Set the MII Management Clock (MDC) - no faster than 2.5 MHz */
        writel(MIIMCFG_CLKSEL_DIV40, &mii_regs->mcfg.raw);
 
        /* Wait for the operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
        return 0;
 }