writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
/* wait till busy */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ CONFIG_SYS_HZ, false);
/* turn controller ON to access PHY over MII */
writel(ETHCON_ON, &ectl_p->con1.set);
writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
/* wait till busy */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ CONFIG_SYS_HZ, false);
/* decrement received buffcnt to zero. */
while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
mdelay(10);
/* wait until everything is down */
- wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
- 2 * CONFIG_SYS_HZ, false);
+ wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+ 2 * CONFIG_SYS_HZ, false);
/* clear any existing interrupt event */
writel(0xffffffff, &ectl_p->irq.clr);