net: ravb: Initialize PHY in probe() once
[oweals/u-boot.git] / drivers / net / pic32_eth.c
index 0b89911f04a2b13c433bd5a626c1a0e6fc823a71..7129372790ef29465fb0bd037be0e91227ddcc35 100644 (file)
@@ -64,8 +64,8 @@ static int pic32_mii_init(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
 
        /* turn controller ON to access PHY over MII */
        writel(ETHCON_ON, &ectl_p->con1.set);
@@ -239,8 +239,8 @@ static void pic32_ctrl_reset(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
        /* decrement received buffcnt to zero. */
        while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
                writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
@@ -375,8 +375,8 @@ static void pic32_eth_stop(struct udevice *dev)
        mdelay(10);
 
        /* wait until everything is down */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    2 * CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         2 * CONFIG_SYS_HZ, false);
 
        /* clear any existing interrupt event */
        writel(0xffffffff, &ectl_p->irq.clr);