ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULP

[oweals/u-boot.git] / drivers / net / pic32_eth.c

diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
index 0b89911f04a2b13c433bd5a626c1a0e6fc823a71..5c706c04c5eb3360fd33a9dab572643ab8daba43 100644 (file)
--- a/drivers/net/pic32_eth.c
+++ b/drivers/net/pic32_eth.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  */
 #include <common.h>
 #include <errno.h>
@@ -64,8 +63,8 @@ static int pic32_mii_init(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
 
        /* turn controller ON to access PHY over MII */
        writel(ETHCON_ON, &ectl_p->con1.set);
@@ -239,8 +238,8 @@ static void pic32_ctrl_reset(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
        /* decrement received buffcnt to zero. */
        while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
                writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
@@ -375,8 +374,8 @@ static void pic32_eth_stop(struct udevice *dev)
        mdelay(10);
 
        /* wait until everything is down */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    2 * CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         2 * CONFIG_SYS_HZ, false);
 
        /* clear any existing interrupt event */
        writel(0xffffffff, &ectl_p->irq.clr);