+// SPDX-License-Identifier: GPL-2.0+
/*
* Cortina CS4315/CS4340 10G PHY drivers
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*
*/
#include <config.h>
#include <common.h>
+#include <log.h>
#include <malloc.h>
#include <linux/ctype.h>
+#include <linux/delay.h>
#include <linux/string.h>
#include <linux/err.h>
#include <phy.h>
#error The Cortina PHY needs 10G support
#endif
+#ifndef CORTINA_NO_FW_UPLOAD
struct cortina_reg_config cortina_reg_cfg[] = {
/* CS4315_enable_sr_mode */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
+#ifdef CONFIG_BLK
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
+ addr);
+#else
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
addr);
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512);
+#endif
}
#endif
phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
}
}
+#endif
int cs4340_phy_init(struct phy_device *phydev)
{
+#ifndef CORTINA_NO_FW_UPLOAD
int timeout = 100; /* 100ms */
+#endif
int reg_value;
+ /*
+ * Cortina phy has provision to store
+ * phy firmware in attached dedicated EEPROM.
+ * Boards designed with EEPROM attached to Cortina
+ * does not require FW upload.
+ */
+#ifndef CORTINA_NO_FW_UPLOAD
/* step1: BIST test */
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
/* setp2: upload ucode */
cs4340_upload_firmware(phydev);
+#endif
reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
if (reg_value) {
debug("%s checksum status failed.\n", __func__);
return 0;
}
+int cs4223_phy_init(struct phy_device *phydev)
+{
+ int reg_value;
+
+ reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
+ if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
+ printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
+ return -ENOSYS;
+ }
+
+ return 0;
+}
+
+int cs4223_config(struct phy_device *phydev)
+{
+ return cs4223_phy_init(phydev);
+}
+
+int cs4223_probe(struct phy_device *phydev)
+{
+ phydev->flags = PHY_FLAG_BROKEN_RESET;
+ return 0;
+}
+
+int cs4223_startup(struct phy_device *phydev)
+{
+ phydev->link = 1;
+ phydev->speed = SPEED_10000;
+ phydev->duplex = DUPLEX_FULL;
+ return 0;
+}
+
struct phy_driver cs4340_driver = {
.name = "Cortina CS4315/CS4340",
.uid = PHY_UID_CS4340,
.shutdown = &gen10g_shutdown,
};
+struct phy_driver cs4223_driver = {
+ .name = "Cortina CS4223",
+ .uid = PHY_UID_CS4223,
+ .mask = 0x0ffff00f,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
+ MDIO_DEVS_AN),
+ .config = &cs4223_config,
+ .probe = &cs4223_probe,
+ .startup = &cs4223_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
int phy_cortina_init(void)
{
phy_register(&cs4340_driver);
+ phy_register(&cs4223_driver);
return 0;
}
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
- bool is_cortina_phy = false;
-
- switch (addr) {
-#ifdef CORTINA_PHY_ADDR1
- case CORTINA_PHY_ADDR1:
-#endif
-#ifdef CORTINA_PHY_ADDR2
- case CORTINA_PHY_ADDR2:
-#endif
-#ifdef CORTINA_PHY_ADDR3
- case CORTINA_PHY_ADDR3:
-#endif
-#ifdef CORTINA_PHY_ADDR4
- case CORTINA_PHY_ADDR4:
-#endif
- is_cortina_phy = true;
- break;
- default:
- break;
- }
/* Cortina PHY has non-standard offset of PHY ID registers */
- if (is_cortina_phy)
- phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
- else
- phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
+ phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
+ if (phy_reg < 0)
+ return -EIO;
+ *phy_id = (phy_reg & 0xffff) << 16;
+ phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
if (phy_reg < 0)
return -EIO;
+ *phy_id |= (phy_reg & 0xffff);
- *phy_id = (phy_reg & 0xffff) << 16;
- if (is_cortina_phy)
- phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
- else
- phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+ if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
+ return 0;
+ /*
+ * If Cortina PHY not detected,
+ * try generic way to find PHY ID registers
+ */
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
if (phy_reg < 0)
return -EIO;
+ *phy_id = (phy_reg & 0xffff) << 16;
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+ if (phy_reg < 0)
+ return -EIO;
*phy_id |= (phy_reg & 0xffff);
return 0;