SPDX: Convert all of our single license tags to Linux Kernel style

[oweals/u-boot.git] / drivers / net / phy / cortina.c

diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 3a2b3bba995282ebd8a96fb61d9ad742df5c246b..9b60d1aac5f22574e3837b6ded95905e799c93b1 100644 (file)
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -1,9 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Cortina CS4315/CS4340 10G PHY drivers
  *
- * SPDX-License-Identifier:     GPL-2.0+
- *
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  */
 
@@ -27,6 +27,7 @@
 #error The Cortina PHY needs 10G support
 #endif
 
+#ifndef CORTINA_NO_FW_UPLOAD
 struct cortina_reg_config cortina_reg_cfg[] = {
        /* CS4315_enable_sr_mode */
        {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
@@ -139,8 +140,9 @@ void cs4340_upload_firmware(struct phy_device *phydev)
        size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
 
        addr = malloc(CONFIG_CORTINA_FW_LENGTH);
-       ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
-                      &fw_length, (u_char *)addr);
+       ret = nand_read(get_nand_dev_by_index(0),
+                       (loff_t)CONFIG_CORTINA_FW_ADDR,
+                       &fw_length, (u_char *)addr);
        if (ret == -EUCLEAN) {
                printf("NAND read of Cortina firmware at 0x%x failed %d\n",
                       CONFIG_CORTINA_FW_ADDR, ret);
@@ -174,9 +176,8 @@ void cs4340_upload_firmware(struct phy_device *phydev)
                printf("MMC read: dev # %u, block # %u, count %u ...\n",
                       dev, blk, cnt);
                mmc_init(mmc);
-               (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
-               /* flush cache after read */
-               flush_cache((ulong)addr, cnt * 512);
+               (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+                                               addr);
        }
 #endif
 
@@ -215,12 +216,22 @@ void cs4340_upload_firmware(struct phy_device *phydev)
                phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
        }
 }
+#endif
 
 int cs4340_phy_init(struct phy_device *phydev)
 {
+#ifndef CORTINA_NO_FW_UPLOAD
        int timeout = 100;  /* 100ms */
+#endif
        int reg_value;
 
+       /*
+        * Cortina phy has provision to store
+        * phy firmware in attached dedicated EEPROM.
+        * Boards designed with EEPROM attached to Cortina
+        * does not require FW upload.
+        */
+#ifndef CORTINA_NO_FW_UPLOAD
        /* step1: BIST test */
        phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL,     0x0004);
        phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
@@ -241,6 +252,7 @@ int cs4340_phy_init(struct phy_device *phydev)
 
        /* setp2: upload ucode */
        cs4340_upload_firmware(phydev);
+#endif
        reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
        if (reg_value) {
                debug("%s checksum status failed.\n", __func__);
@@ -256,6 +268,12 @@ int cs4340_config(struct phy_device *phydev)
        return 0;
 }
 
+int cs4340_probe(struct phy_device *phydev)
+{
+       phydev->flags = PHY_FLAG_BROKEN_RESET;
+       return 0;
+}
+
 int cs4340_startup(struct phy_device *phydev)
 {
        phydev->link = 1;
@@ -275,6 +293,7 @@ struct phy_driver cs4340_driver = {
                 MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
                 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
        .config = &cs4340_config,
+       .probe  = &cs4340_probe,
        .startup = &cs4340_startup,
        .shutdown = &gen10g_shutdown,
 };
@@ -288,45 +307,33 @@ int phy_cortina_init(void)
 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 {
        int phy_reg;
-       bool is_cortina_phy = false;
-
-       switch (addr) {
-#ifdef CORTINA_PHY_ADDR1
-       case CORTINA_PHY_ADDR1:
-#endif
-#ifdef CORTINA_PHY_ADDR2
-       case CORTINA_PHY_ADDR2:
-#endif
-#ifdef CORTINA_PHY_ADDR3
-       case CORTINA_PHY_ADDR3:
-#endif
-#ifdef CORTINA_PHY_ADDR4
-       case CORTINA_PHY_ADDR4:
-#endif
-               is_cortina_phy = true;
-               break;
-       default:
-               break;
-       }
 
        /* Cortina PHY has non-standard offset of PHY ID registers */
-       if (is_cortina_phy)
-               phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
-       else
-               phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
+       phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
+       if (phy_reg < 0)
+               return -EIO;
+       *phy_id = (phy_reg & 0xffff) << 16;
 
+       phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
        if (phy_reg < 0)
                return -EIO;
+       *phy_id |= (phy_reg & 0xffff);
 
-       *phy_id = (phy_reg & 0xffff) << 16;
-       if (is_cortina_phy)
-               phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
-       else
-               phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+       if (*phy_id == PHY_UID_CS4340)
+               return 0;
 
+       /*
+        * If Cortina PHY not detected,
+        * try generic way to find PHY ID registers
+        */
+       phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
        if (phy_reg < 0)
                return -EIO;
+       *phy_id = (phy_reg & 0xffff) << 16;
 
+       phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+       if (phy_reg < 0)
+               return -EIO;
        *phy_id |= (phy_reg & 0xffff);
 
        return 0;