/* Switch pcnet to 32bit mode */
pcnet_write_bcr(dev, 20, 2);
-#ifdef CONFIG_PN62
- /* Setup LED registers */
- val = pcnet_read_bcr(dev, 2) | 0x1000;
- pcnet_write_bcr(dev, 2, val); /* enable LEDPE */
- pcnet_write_bcr(dev, 4, 0x5080); /* 100MBit */
- pcnet_write_bcr(dev, 5, 0x40c0); /* LNKSE */
- pcnet_write_bcr(dev, 6, 0x4090); /* TX Activity */
- pcnet_write_bcr(dev, 7, 0x4084); /* RX Activity */
-#endif
-
/* Set/reset autoselect bit */
val = pcnet_read_bcr(dev, 2) & ~2;
val |= 2;
val |= 0x20;
pcnet_write_bcr(dev, 32, val);
+ /*
+ * Enable NOUFLO on supported controllers, with the transmit
+ * start point set to the full packet. This will cause entire
+ * packets to be buffered by the ethernet controller before
+ * transmission, eliminating underflows which are common on
+ * slower devices. Controllers which do not support NOUFLO will
+ * simply be left with a larger transmit FIFO threshold.
+ */
+ val = pcnet_read_bcr(dev, 18);
+ val |= 1 << 11;
+ pcnet_write_bcr(dev, 18, val);
+ val = pcnet_read_csr(dev, 80);
+ val |= 0x3 << 10;
+ pcnet_write_csr(dev, 80, val);
+
/*
* We only maintain one structure because the drivers will never
* be used concurrently. In 32bit mode the RX and TX ring entries