#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
-#if defined(CONFIG_CMD_NET) \
- && defined(CONFIG_NET_MULTI) && defined(CONFIG_NS8382X)
-
/* defines */
#define DSIZE 0x00000FFF
#define ETH_ALEN 6
Read and write MII registers using software-generated serial MDIO
protocol. See the MII specifications or DP83840A data sheet for details.
- The maximum data clock rate is 2.5 Mhz. To meet minimum timing we
+ The maximum data clock rate is 2.5 MHz. To meet minimum timing we
must flush writes to the PCI bus with a PCI read. */
#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
if (i >= TOUT_LOOP) {
- printf ("%s: tx error buffer not ready: txd.cmdsts %#X\n",
+ printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
dev->name, tx_stat);
goto Done;
}
}
if (!(tx_stat & DescPktOK)) {
- printf("ns8382x_send: Transmit error, Tx status %X.\n", tx_stat);
+ printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
goto Done;
}
#ifdef NS8382X_DEBUG
/* Restore PME enable bit */
OUTL(dev, SavedClkRun, ClkRun);
}
-
-#endif