net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle

[oweals/u-boot.git] / drivers / net / mvgbe.h

diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index 3de98d01bd9dc44434b669c716765c76c6f22856..44541c0a85e302fb87b4024268615d70048a789d 100644 (file)
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2009
  * Marvell Semiconductor <www.marvell.com>
@@ -5,24 +6,6 @@
  *
  * based on - Driver for MV64360X ethernet ports
  * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
  */
 
 #ifndef __MVGBE_H__
@@ -47,7 +30,9 @@
 #define RXUQ   0 /* Used Rx queue */
 #define TXUQ   0 /* Used Rx queue */
 
+#ifndef CONFIG_DM_ETH
 #define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
+#endif
 #define MVGBE_REG_WR(adr, val)         writel(val, &adr)
 #define MVGBE_REG_RD(adr)              readl(&adr)
 #define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
@@ -84,6 +69,7 @@
        MVGBE_TX_BURST_SIZE_16_64BIT)
 
 /* Default port serial control value */
+#ifndef PORT_SERIAL_CONTROL_VALUE
 #define PORT_SERIAL_CONTROL_VALUE              ( \
        MVGBE_FORCE_LINK_PASS                   | \
        MVGBE_DIS_AUTO_NEG_FOR_DUPLX            | \
@@ -101,6 +87,7 @@
        MVGBE_CLR_EXT_LOOPBACK                  | \
        MVGBE_SET_FULL_DUPLEX_MODE              | \
        MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+#endif
 
 /* Tx WRR confoguration macros */
 #define PORT_MAX_TRAN_UNIT     0x24    /* MTU register (default) 9KByte */
@@ -231,6 +218,7 @@
 
 /* SMI register fields */
 #define MVGBE_PHY_SMI_TIMEOUT          10000
+#define MVGBE_PHY_SMI_TIMEOUT_MS       1000
 #define MVGBE_PHY_SMI_DATA_OFFS                0       /* Data */
 #define MVGBE_PHY_SMI_DATA_MASK                (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
 #define MVGBE_PHY_SMI_DEV_ADDR_OFFS    16      /* PHY device address */
@@ -493,13 +481,27 @@ struct mvgbe_txdesc {
 
 /* port device data struct */
 struct mvgbe_device {
+#ifndef CONFIG_DM_ETH
        struct eth_device dev;
+#endif
        struct mvgbe_registers *regs;
        struct mvgbe_txdesc *p_txdesc;
        struct mvgbe_rxdesc *p_rxdesc;
        struct mvgbe_rxdesc *p_rxdesc_curr;
        u8 *p_rxbuf;
        u8 *p_aligned_txbuf;
+
+#ifdef CONFIG_DM_ETH
+       phy_interface_t phy_interface;
+       unsigned int link;
+       unsigned int duplex;
+       unsigned int speed;
+
+       int init;
+       int phyaddr;
+       struct phy_device *phydev;
+       struct mii_dev *bus;
+#endif
 };
 
 #endif /* __MVGBE_H__ */