mmc: fsl_esdhc: workaround for hardware 3.3v IO reliability issue
[oweals/u-boot.git] / drivers / net / ldpaa_eth / ls1088a.c
index 780a23998ad944dcc2c4bfc25eb59627852f4bb0..54cb16e51b1f3d1bd6af6f5760b0235170d51728 100644 (file)
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2017 NXP
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <phy.h>
@@ -9,6 +8,7 @@
 #include <asm/io.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
+#include <linux/mii.h>
 
 u32 dpmac_to_devdisr[] = {
        [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
@@ -94,7 +94,7 @@ void fsl_rgmii_init(void)
        u32 ec;
 
 #ifdef CONFIG_SYS_FSL_EC1
-       ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
+       ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
                & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
        ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
 
@@ -103,7 +103,7 @@ void fsl_rgmii_init(void)
 #endif
 
 #ifdef CONFIG_SYS_FSL_EC2
-       ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
+       ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
                & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
        ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;