+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <phy.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
+#include <linux/mii.h>
u32 dpmac_to_devdisr[] = {
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
u32 ec;
#ifdef CONFIG_SYS_FSL_EC1
- ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
+ ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
#endif
#ifdef CONFIG_SYS_FSL_EC2
- ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
+ ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;