#include <common.h>
-#if defined(CONFIG_CMD_NET) \
- && defined(CONFIG_NET_MULTI) && defined(CONFIG_INCA_IP_SWITCH)
-
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/inca-ip.h>
#include <asm/addrspace.h>
printf("Leaving inca_switch_initialize()\n");
#endif
- return 1;
+ return 0;
}
/* Initialize the descriptor rings.
*/
for (i = 0; i < NUM_RX_DESC; i++) {
- inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
+ inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
memset(rx_desc, 0, sizeof(rx_ring[i]));
/* Set maximum size of receive buffer.
/* Let the last descriptor point to the first
* one.
*/
- rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
+ rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
} else {
/* Set the address of the next descriptor.
*/
- rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
+ rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
}
- rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
+ rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
}
#if 0
#endif
for (i = 0; i < NUM_TX_DESC; i++) {
- inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
+ inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
memset(tx_desc, 0, sizeof(tx_ring[i]));
/* Let the last descriptor point to the
* first one.
*/
- tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
+ tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
} else {
/* Set the address of the next descriptor.
*/
- tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
+ tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
}
}
int res = -1;
u32 command;
u32 regValue;
- inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
+ inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
#if 0
printf("Entered inca_switch_send()\n");
}
if (tx_old_hold >= 0) {
- KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
+ ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
}
tx_old_hold = tx_hold;
tx_desc->TxDataPtr = (u32)packet;
tx_desc->params.field.NBA = length;
- KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
+ ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
tx_hold = tx_new;
tx_new = (tx_new + 1) % NUM_TX_DESC;
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
#if 1
- for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
+ for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
if (i >= TOUT_LOOP) {
printf("%s: tx buffer not ready\n", dev->name);
goto Done;
#endif
for (;;) {
- rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
+ rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
if (rx_desc->status.field.C == 0) {
break;
#if 0
printf("Received %d bytes\n", length);
#endif
- NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
+ NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
} else {
#if 1
printf("Zero length!!!\n");
}
- KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
+ ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
rx_hold = rx_new;
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (6 << 16)); /* PHY_ANER */
+ (6 << 16)); /* MII_EXPANSION */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
} while (phyReg6 & (1 << 31));
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (4 << 16)); /* PHY_ANAR */
+ (4 << 16)); /* MII_ADVERTISE */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
} while (phyReg4 & (1 << 31));
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (5 << 16)); /* PHY_ANLPAR */
+ (5 << 16)); /* MII_LPA */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
} while (phyReg5 & (1 << 31));
return -1;
}
#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
-
-#endif