* Copyright (C) 2018, IBM Corporation.
*/
+#include <clk.h>
#include <dm.h>
#include <miiphy.h>
-#include <malloc.h>
#include <net.h>
+#include <wait_bit.h>
#include <linux/io.h>
-#include <asm/dma-mapping.h>
#include <linux/iopoll.h>
#include "ftgmac100.h"
-#define ETH_ZLEN 60
-#define CFG_XBUF_SIZE 1536
+/* Min frame ethernet frame size without FCS */
+#define ETH_ZLEN 60
-/* RBSR - hw default init value is also 0x640 */
-#define RBSR_DEFAULT_VALUE 0x640
+/* Receive Buffer Size Register - HW default is 0x640 */
+#define FTGMAC100_RBSR_DEFAULT 0x640
/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
#define PKTBUFSTX 4 /* must be power of 2 */
+/* Timeout for transmit */
+#define FTGMAC100_TX_TIMEOUT_MS 1000
+
/* Timeout for a mdio read/write operation */
#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
*/
#define MDC_CYCTHR 0x34
+/*
+ * ftgmac100 model variants
+ */
+enum ftgmac100_model {
+ FTGMAC100_MODEL_FARADAY,
+ FTGMAC100_MODEL_ASPEED,
+};
+
/**
* struct ftgmac100_data - private data for the FTGMAC100 driver
*
* @bus: The mdio bus
* @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
* @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @clks: The bulk of clocks assigned to the device in the DT
+ * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
+ * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
*/
struct ftgmac100_data {
struct ftgmac100 *iobase;
- ulong txdes_dma;
- struct ftgmac100_txdes *txdes;
- ulong rxdes_dma;
- struct ftgmac100_rxdes *rxdes;
+ struct ftgmac100_txdes txdes[PKTBUFSTX];
+ struct ftgmac100_rxdes rxdes[PKTBUFSRX];
int tx_index;
int rx_index;
struct mii_dev *bus;
u32 phy_mode;
u32 max_speed;
+
+ struct clk_bulk clks;
+
+ /* End of RX/TX ring buffer bits. Depend on model */
+ u32 rxdes0_edorr_mask;
+ u32 txdes0_edotr_mask;
};
/*
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct phy_device *phydev = priv->phydev;
- struct ftgmac100_txdes *txdes;
- struct ftgmac100_rxdes *rxdes;
unsigned int maccr;
- void *buf;
+ ulong start, end;
int ret;
int i;
ftgmac100_reset(priv);
- if (!priv->txdes) {
- txdes = dma_alloc_coherent(
- sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
- if (!txdes)
- panic("ftgmac100: out of memory\n");
- memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
- priv->txdes = txdes;
- }
- txdes = priv->txdes;
-
- if (!priv->rxdes) {
- rxdes = dma_alloc_coherent(
- sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
- if (!rxdes)
- panic("ftgmac100: out of memory\n");
- memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
- priv->rxdes = rxdes;
- }
- rxdes = priv->rxdes;
-
/* set the ethernet address */
ftgmac100_set_mac(priv, plat->enetaddr);
priv->tx_index = 0;
priv->rx_index = 0;
- txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
- rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
-
for (i = 0; i < PKTBUFSTX; i++) {
- /* TXBUF_BADR */
- if (!txdes[i].txdes2) {
- buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
- if (!buf)
- panic("ftgmac100: out of memory\n");
- txdes[i].txdes3 = virt_to_phys(buf);
- txdes[i].txdes2 = (uint)buf;
- }
- txdes[i].txdes1 = 0;
+ priv->txdes[i].txdes3 = 0;
+ priv->txdes[i].txdes0 = 0;
}
+ priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
+
+ start = (ulong)&priv->txdes[0];
+ end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
for (i = 0; i < PKTBUFSRX; i++) {
- /* RXBUF_BADR */
- if (!rxdes[i].rxdes2) {
- buf = net_rx_packets[i];
- rxdes[i].rxdes3 = virt_to_phys(buf);
- rxdes[i].rxdes2 = (uint)buf;
- }
- rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+ priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+ priv->rxdes[i].rxdes0 = 0;
}
+ priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
+
+ start = (ulong)&priv->rxdes[0];
+ end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
/* transmit ring */
- writel(priv->txdes_dma, &ftgmac100->txr_badr);
+ writel((u32)priv->txdes, &ftgmac100->txr_badr);
/* receive ring */
- writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
+ writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
/* config receive buffer size register */
- writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
+ writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
/* enable transmitter, receiver */
maccr = FTGMAC100_MACCR_TXMAC_EN |
{
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
- /* Release buffer to DMA */
+ /* Release buffer to DMA and flush descriptor */
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+ flush_dcache_range(des_start, des_end);
/* Move to next descriptor */
priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct ftgmac100_data *priv = dev_get_priv(dev);
- struct ftgmac100_rxdes *curr_des;
+ struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
unsigned short rxlen;
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ ulong data_start = curr_des->rxdes3;
+ ulong data_end;
- curr_des = &priv->rxdes[priv->rx_index];
+ invalidate_dcache_range(des_start, des_end);
if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
- return -1;
+ return -EAGAIN;
if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
FTGMAC100_RXDES0_CRC_ERR |
FTGMAC100_RXDES0_FTL |
FTGMAC100_RXDES0_RUNT |
FTGMAC100_RXDES0_RX_ODD_NB)) {
- return -1;
+ return -EAGAIN;
}
rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
debug("%s(): RX buffer %d, %x received\n",
__func__, priv->rx_index, rxlen);
- /* invalidate d-cache */
- dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
+ /* Invalidate received data */
+ data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start, data_end);
+ *packetp = (uchar *)data_start;
- /* pass the packet up to the protocol layers. */
- net_process_received_packet((void *)curr_des->rxdes2, rxlen);
+ return rxlen;
+}
- /* release buffer to DMA */
- curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+static u32 ftgmac100_read_txdesc(const void *desc)
+{
+ const struct ftgmac100_txdes *txdes = desc;
+ ulong des_start = (ulong)txdes;
+ ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
- priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
+ invalidate_dcache_range(des_start, des_end);
- return 0;
+ return txdes->txdes0;
}
+BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
+
/*
* Send a data block via Ethernet
*/
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ ulong data_start;
+ ulong data_end;
+ int rc;
+
+ invalidate_dcache_range(des_start, des_end);
if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
- debug("%s(): no TX descriptor available\n", __func__);
- return -1;
+ dev_err(dev, "no TX descriptor available\n");
+ return -EPERM;
}
debug("%s(%x, %x)\n", __func__, (int)packet, length);
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
- memcpy((void *)curr_des->txdes2, (void *)packet, length);
- dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
+ curr_des->txdes3 = (unsigned int)packet;
+
+ /* Flush data to be sent */
+ data_start = curr_des->txdes3;
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ flush_dcache_range(data_start, data_end);
- /* only one descriptor on TXBUF */
- curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
+ /* Only one segment on TXBUF */
+ curr_des->txdes0 &= priv->txdes0_edotr_mask;
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
FTGMAC100_TXDES0_LTS |
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
FTGMAC100_TXDES0_TXDMA_OWN ;
- /* start transmit */
+ /* Flush modified buffer descriptor */
+ flush_dcache_range(des_start, des_end);
+
+ /* Start transmit */
writel(1, &ftgmac100->txpd);
+ rc = wait_for_bit_ftgmac100_txdone(curr_des,
+ FTGMAC100_TXDES0_TXDMA_OWN, false,
+ FTGMAC100_TX_TIMEOUT_MS, true);
+ if (rc)
+ return rc;
+
debug("%s(): packet sent\n", __func__);
+ /* Move to next descriptor */
priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
return 0;
static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
pdata->iobase = devfdt_get_addr(dev);
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
- return 0;
+ if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
+ priv->rxdes0_edorr_mask = BIT(30);
+ priv->txdes0_edotr_mask = BIT(30);
+ } else {
+ priv->rxdes0_edorr_mask = BIT(15);
+ priv->txdes0_edotr_mask = BIT(15);
+ }
+
+ return clk_get_bulk(dev, &priv->clks);
}
static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret)
+ goto out;
+
ret = ftgmac100_mdio_init(dev);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
}
out:
+ if (ret)
+ clk_release_bulk(&priv->clks);
+
return ret;
}
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+ clk_release_bulk(&priv->clks);
return 0;
}
};
static const struct udevice_id ftgmac100_ids[] = {
- { .compatible = "faraday,ftgmac100" },
+ { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
+ { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
{ }
};
projects / oweals / u-boot.git / blobdiff