serial: add BCM283x mini UART driver

[oweals/u-boot.git] / drivers / net / fm / eth.c

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 728718e86e9b16a4db82a3ad36e0e9132e6f6528..eb8e93618f27614aad40287f0ad794e2273c977b 100644 (file)
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -13,8 +13,8 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_dtsec.h>
+#include <fsl_tgec.h>
 #include <fsl_memac.h>
 
 #include "fm.h"
@@ -41,28 +41,35 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
        bus.priv = priv->mac->phyregs;
        bool sgmii_2500 = (priv->enet_if ==
                        PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+       int i = 0;
 
+qsgmii_loop:
        /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
        value = PHY_SGMII_IF_MODE_SGMII;
        if (!sgmii_2500)
                value |= PHY_SGMII_IF_MODE_AN;
 
-       memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+       memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
 
        /* Dev ability according to SGMII specification */
        value = PHY_SGMII_DEV_ABILITY_SGMII;
-       memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+       memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
 
        /* Adjust link timer for SGMII  -
        1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-       memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
-       memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+       memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+       memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
 
        /* Restart AN */
        value = PHY_SGMII_CR_DEF_VAL;
        if (!sgmii_2500)
                value |= PHY_SGMII_CR_RESET_AN;
-       memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+       memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
+
+       if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+               i++;
+               goto qsgmii_loop;
+       }
 #else
        struct dtsec *regs = priv->mac->base;
        struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,10 +98,12 @@ static void dtsec_init_phy(struct eth_device *dev)
 #endif
 
        if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+           fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
            fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
                dtsec_configure_serdes(fm_eth);
 }
 
+#ifdef CONFIG_PHYLIB
 static int tgec_is_fibre(struct eth_device *dev)
 {
        struct fm_eth *fm = dev->priv;
@@ -105,6 +114,7 @@ static int tgec_is_fibre(struct eth_device *dev)
        return hwconfig_arg_cmp(phyopt, "xfi");
 }
 #endif
+#endif
 
 static u16 muram_readw(u16 *addr)
 {
@@ -483,8 +493,10 @@ static void fm_eth_halt(struct eth_device *dev)
        /* disable bmi Rx port */
        bmi_rx_port_disable(fm_eth->rx_port);
 
+#ifdef CONFIG_PHYLIB
        if (fm_eth->phydev)
                phy_shutdown(fm_eth->phydev);
+#endif
 }
 
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
@@ -658,13 +670,15 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 static int init_phy(struct eth_device *dev)
 {
        struct fm_eth *fm_eth = dev->priv;
+#ifdef CONFIG_PHYLIB
        struct phy_device *phydev = NULL;
        u32 supported;
+#endif
 
-#ifdef CONFIG_PHYLIB
        if (fm_eth->type == FM_ETH_1G_E)
                dtsec_init_phy(dev);
 
+#ifdef CONFIG_PHYLIB
        if (fm_eth->bus) {
                phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
                                        fm_eth->enet_if);