#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
#define FEC_ECNTRL_SPEED 0x00000020
#define FEC_ECNTRL_DBSWAP 0x00000100
+#define FEC_ECNTRL_TXC_DLY 0x00010000 /* TXC delayed */
+#define FEC_ECNTRL_RXC_DLY 0x00020000 /* RXC delayed */
#define FEC_X_WMRK_STRFWD 0x00000100
#ifdef CONFIG_DM_REGULATOR
struct udevice *phy_supply;
#endif
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc phy_reset_gpio;
uint32_t reset_delay;
+ uint32_t reset_post_delay;
#endif
#ifdef CONFIG_DM_ETH
u32 interface;
#endif
struct clk ipg_clk;
+ struct clk ahb_clk;
+ struct clk clk_enet_out;
+ struct clk clk_ref;
+ struct clk clk_ptp;
u32 clk_rate;
};
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
/**
* @brief Numbers of buffer descriptors for receiving
*