FEC: Add support for iMX28 quirks

[oweals/u-boot.git] / drivers / net / fec_mxc.c

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3c593aaaf50cf446c19e1e46fbc30c49c1419ee4..b05a4c0c9a7b383a23df14f81d732fe61a765feb 100644 (file)
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -42,6 +42,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define        CONFIG_FEC_XCV_TYPE     MII100
 #endif
 
+/*
+ * The i.MX28 operates with packets in big endian. We need to swap them before
+ * sending and after receiving.
+ */
+#ifdef CONFIG_MX28
+#define        CONFIG_FEC_MXC_SWAP_PACKET
+#endif
+
 #undef DEBUG
 
 struct nbuf {
@@ -51,6 +59,32 @@ struct nbuf {
        uint8_t head[16];       /**< MAC header(6 + 6 + 2) + 2(aligned) */
 };
 
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+static void swap_packet(uint32_t *packet, int length)
+{
+       int i;
+
+       for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
+               packet[i] = __swab32(packet[i]);
+}
+#endif
+
+/*
+ * The i.MX28 has two ethernet interfaces, but they are not equal.
+ * Only the first one can access the MDIO bus.
+ */
+#ifdef CONFIG_MX28
+static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
+{
+       return (struct ethernet_regs *)MXS_ENET0_BASE;
+}
+#else
+static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
+{
+       return fec->eth;
+}
+#endif
+
 /*
  * MII-interface related functions
  */
@@ -59,7 +93,7 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
 {
        struct eth_device *edev = eth_get_dev_by_name(dev);
        struct fec_priv *fec = (struct fec_priv *)edev->priv;
-       struct ethernet_regs *eth = fec->eth;
+       struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
 
        uint32_t reg;           /* convenient holder for the PHY register */
        uint32_t phy;           /* convenient holder for the PHY */
@@ -109,7 +143,7 @@ static void fec_mii_setspeed(struct fec_priv *fec)
         */
        writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
                        &fec->eth->mii_speed);
-       debug("fec_init: mii_speed %#lx\n",
+       debug("fec_init: mii_speed %08x\n",
                        readl(&fec->eth->mii_speed));
 }
 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
@@ -117,7 +151,7 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
 {
        struct eth_device *edev = eth_get_dev_by_name(dev);
        struct fec_priv *fec = (struct fec_priv *)edev->priv;
-       struct ethernet_regs *eth = fec->eth;
+       struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
 
        uint32_t reg;           /* convenient holder for the PHY register */
        uint32_t phy;           /* convenient holder for the PHY */
@@ -153,6 +187,7 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
 static int miiphy_restart_aneg(struct eth_device *dev)
 {
        struct fec_priv *fec = (struct fec_priv *)dev->priv;
+       int ret = 0;
 
        /*
         * Wake up from sleep if necessary
@@ -173,7 +208,11 @@ static int miiphy_restart_aneg(struct eth_device *dev)
                        LPA_10HALF | PHY_ANLPAR_PSB_802_3);
        miiphy_write(dev->name, fec->phy_id, MII_BMCR,
                        BMCR_ANENABLE | BMCR_ANRESTART);
-       return 0;
+
+       if (fec->mii_postcall)
+               ret = fec->mii_postcall(fec->phy_id);
+
+       return ret;
 }
 
 static int miiphy_wait_aneg(struct eth_device *dev)
@@ -567,6 +606,9 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
         * Note: We are always using the first buffer for transmission,
         * the second will be empty and only used to stop the DMA engine
         */
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+       swap_packet((uint32_t *)packet, length);
+#endif
        writew(length, &fec->tbd_base[fec->tbd_index].data_length);
        writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
        /*
@@ -624,7 +666,7 @@ static int fec_recv(struct eth_device *dev)
         */
        ievent = readl(&fec->eth->ievent);
        writel(ievent, &fec->eth->ievent);
-       debug("fec_recv: ievent 0x%x\n", ievent);
+       debug("fec_recv: ievent 0x%lx\n", ievent);
        if (ievent & FEC_IEVENT_BABR) {
                fec_halt(dev);
                fec_init(dev, fec->bd);
@@ -663,6 +705,9 @@ static int fec_recv(struct eth_device *dev)
                        /*
                         *  Fill the buffer and pass it to upper layers
                         */
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+                       swap_packet((uint32_t *)frame->data, frame_length);
+#endif
                        memcpy(buff, frame->data, frame_length);
                        NetReceive(buff, frame_length);
                        len = frame_length;
@@ -690,18 +735,22 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
        struct eth_device *edev;
        struct fec_priv *fec;
        unsigned char ethaddr[6];
+       uint32_t start;
+       int ret = 0;
 
        /* create and fill edev struct */
        edev = (struct eth_device *)malloc(sizeof(struct eth_device));
        if (!edev) {
                puts("fec_mxc: not enough malloc memory for eth_device\n");
-               return -ENOMEM;
+               ret = -ENOMEM;
+               goto err1;
        }
 
        fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
        if (!fec) {
                puts("fec_mxc: not enough malloc memory for fec_priv\n");
-               return -ENOMEM;
+               ret = -ENOMEM;
+               goto err2;
        }
 
        memset(edev, 0, sizeof(*edev));
@@ -721,8 +770,14 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
 
        /* Reset chip. */
        writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
-       while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET)
+       start = get_timer(0);
+       while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
+               if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
+                       printf("FEC MXC: Timeout reseting chip\n");
+                       goto err3;
+               }
                udelay(10);
+       }
 
        /*
         * Set interrupt mask register
@@ -758,11 +813,18 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
        eth_register(edev);
 
        if (fec_get_hwaddr(edev, ethaddr) == 0) {
-               printf("got MAC address from fuse: %pM\n", ethaddr);
+               debug("got MAC address from fuse: %pM\n", ethaddr);
                memcpy(edev->enetaddr, ethaddr, 6);
        }
 
-       return 0;
+       return ret;
+
+err3:
+       free(fec);
+err2:
+       free(edev);
+err1:
+       return ret;
 }
 
 #ifndef        CONFIG_FEC_MXC_MULTI
@@ -786,3 +848,10 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
 
        return lout;
 }
+
+int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
+{
+       struct fec_priv *fec = (struct fec_priv *)dev->priv;
+       fec->mii_postcall = cb;
+       return 0;
+}