Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
Copyright 2011 Freescale Semiconductor, Inc.
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License along with
- this program; if not, write to the Free Software Foundation, Inc., 59
- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- The full GNU General Public License is included in this distribution in the
- file called LICENSE.
+ * SPDX-License-Identifier: GPL-2.0+
Contact Information:
Linux NICS <linux.nics@intel.com>
/* I/O wrapper functions */
#define E1000_WRITE_REG(a, reg, value) \
- (writel((value), ((a)->hw_addr + E1000_##reg)))
+ writel((value), ((a)->hw_addr + E1000_##reg))
#define E1000_READ_REG(a, reg) \
- (readl((a)->hw_addr + E1000_##reg))
+ readl((a)->hw_addr + E1000_##reg)
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
- (writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
+ writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
#define E1000_READ_REG_ARRAY(a, reg, offset) \
- (readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
+ readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
#define E1000_WRITE_FLUSH(a) \
- do { uint32_t x = E1000_READ_REG(a, STATUS); } while (0)
+ do { E1000_READ_REG(a, STATUS); } while (0)
/* Forward declarations of structures used by the shared code */
struct e1000_hw;
/* Internal E1000 helper functions */
struct e1000_hw *e1000_find_card(unsigned int cardnum);
+
+#ifndef CONFIG_E1000_NO_NVM
int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
void e1000_standby_eeprom(struct e1000_hw *hw);
void e1000_release_eeprom(struct e1000_hw *hw);
void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
+#endif
#ifdef CONFIG_E1000_SPI
int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
int argc, char * const argv[]);
#endif
-typedef enum {
- FALSE = 0,
- TRUE = 1
-} boolean_t;
-
/* Enumerated types specific to the e1000 hardware */
/* Media Access Controlers */
typedef enum {
Control and Address */
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
control register */
-#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False
+#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false
Carrier Counter */
#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
Counter */
uint64_t tsctfc;
};
+#ifndef CONFIG_E1000_NO_NVM
struct e1000_eeprom_info {
- e1000_eeprom_type type;
- uint16_t word_size;
- uint16_t opcode_bits;
- uint16_t address_bits;
- uint16_t delay_usec;
- uint16_t page_size;
- boolean_t use_eerd;
- boolean_t use_eewr;
+e1000_eeprom_type type;
+ uint16_t word_size;
+ uint16_t opcode_bits;
+ uint16_t address_bits;
+ uint16_t delay_usec;
+ uint16_t page_size;
+ bool use_eerd;
+ bool use_eewr;
};
+#endif
typedef enum {
e1000_smart_speed_default = 0,
uint32_t io_base;
#endif
uint32_t asf_firmware_present;
+#ifndef CONFIG_E1000_NO_NVM
uint32_t eeprom_semaphore_present;
+#endif
uint32_t swfw_sync_present;
uint32_t swfwhw_semaphore_present;
+#ifndef CONFIG_E1000_NO_NVM
struct e1000_eeprom_info eeprom;
+#endif
e1000_ms_type master_slave;
e1000_ms_type original_master_slave;
e1000_ffe_config ffe_config_state;
#if 0
uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
#endif
- boolean_t disable_polarity_correction;
- boolean_t speed_downgraded;
- boolean_t get_link_status;
- boolean_t tbi_compatibility_en;
- boolean_t tbi_compatibility_on;
- boolean_t fc_strict_ieee;
- boolean_t fc_send_xon;
- boolean_t report_tx_early;
- boolean_t phy_reset_disable;
- boolean_t initialize_hw_bits_disable;
+ bool disable_polarity_correction;
+ bool speed_downgraded;
+ bool get_link_status;
+ bool tbi_compatibility_en;
+ bool tbi_compatibility_on;
+ bool fc_strict_ieee;
+ bool fc_send_xon;
+ bool report_tx_early;
+ bool phy_reset_disable;
+ bool initialize_hw_bits_disable;
#if 0
- boolean_t adaptive_ifs;
- boolean_t ifs_params_forced;
- boolean_t in_ifs_mode;
+ bool adaptive_ifs;
+ bool ifs_params_forced;
+ bool in_ifs_mode;
#endif
e1000_smart_speed smart_speed;
e1000_dsp_config dsp_config_state;
#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
+#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
/* Transmit Descriptor Control */
#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
-/* EEPROM Word Offsets */
-#define EEPROM_COMPAT 0x0003
-#define EEPROM_ID_LED_SETTINGS 0x0004
-#define EEPROM_INIT_CONTROL1_REG 0x000A
-#define EEPROM_INIT_CONTROL2_REG 0x000F
-#define EEPROM_FLASH_VERSION 0x0032
-#define EEPROM_CHECKSUM_REG 0x003F
-
/* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_0000 0x0000
#define ID_LED_RESERVED_FFFF 0xFFFF
* Typical use:
* ...
* if (TBI_ACCEPT) {
- * accept_frame = TRUE;
+ * accept_frame = true;
* e1000_tbi_adjust_stats(adapter, MacAddress);
* frame_length--;
* } else {
- * accept_frame = FALSE;
+ * accept_frame = false;
* }
* ...
*/
#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
-#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
+#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */
#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
#define ADVERTISE_100_FULL 0x0008
#define ADVERTISE_1000_HALF 0x0010
#define ADVERTISE_1000_FULL 0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
#define ICH_FLASH_GFPREG 0x0000
#define ICH_FLASH_HSFSTS 0x0004
#define ICH_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
-#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
/* SPI EEPROM Status Register */
#define PHY_CFG_TIMEOUT 100
#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
-#define E1000_TXDMAC_DPP 0x00000001
#define AUTO_ALL_MODES 0
#ifndef E1000_MASTER_SLAVE
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