Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

[oweals/u-boot.git] / drivers / net / e1000.c

diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 6e8765cf7b61bebc6060e26ef31143d8b784f25b..96e6bb08246df6d27657137b8a649e1605368cda 100644 (file)
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -92,7 +92,10 @@ static struct pci_device_id e1000_supported[] = {
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
@@ -1112,8 +1115,11 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
                if (e1000_get_hw_eeprom_semaphore(hw))
                        return -E1000_ERR_SWFW_SYNC;
 
-               swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
-               if ((swfw_sync & swmask) && !(swfw_sync & fwmask))
+               if (hw->mac_type == e1000_igb)
+                       swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
+               else
+                       swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+               if (!(swfw_sync & (fwmask | swmask)))
                        break;
 
                /* firmware currently using resource (fwmask) */
@@ -1191,7 +1197,7 @@ e1000_read_mac_addr(struct eth_device *nic)
                nic->enetaddr[5] ^= 1;
 
 #ifdef CONFIG_E1000_FALLBACK_MAC
-       if (!is_valid_ether_addr(nic->enetaddr)) {
+       if (!is_valid_ethaddr(nic->enetaddr)) {
                unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
 
                memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
@@ -1374,7 +1380,10 @@ e1000_set_mac_type(struct e1000_hw *hw)
        case E1000_DEV_ID_ICH8_IGP_M:
                hw->mac_type = e1000_ich8lan;
                break;
+       case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
+       case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
        case PCI_DEVICE_ID_INTEL_I210_COPPER:
+       case PCI_DEVICE_ID_INTEL_I211_COPPER:
        case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
        case PCI_DEVICE_ID_INTEL_I210_SERDES:
        case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
@@ -2165,7 +2174,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
                DEBUGOUT("Error, did not detect valid phy.\n");
                return ret_val;
        }
-       DEBUGOUT("Phy ID = %x \n", hw->phy_id);
+       DEBUGOUT("Phy ID = %x\n", hw->phy_id);
 
        /* Set PHY to class A mode (if necessary) */
        ret_val = e1000_set_phy_mode(hw);
@@ -3476,11 +3485,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
                 * some "sticky" (latched) bits.
                 */
                if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
-                       DEBUGOUT("PHY Read Error \n");
+                       DEBUGOUT("PHY Read Error\n");
                        return -E1000_ERR_PHY;
                }
                if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
-                       DEBUGOUT("PHY Read Error \n");
+                       DEBUGOUT("PHY Read Error\n");
                        return -E1000_ERR_PHY;
                }
 
@@ -4429,7 +4438,6 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
 
                if (hw->mac_type >= e1000_82571)
                        mdelay(10);
-
        } else {
                /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
                 * bit to put the PHY into reset. Then, take it out of reset.
@@ -4919,22 +4927,23 @@ void
 fill_rx(struct e1000_hw *hw)
 {
        struct e1000_rx_desc *rd;
-       uint32_t flush_start, flush_end;
+       unsigned long flush_start, flush_end;
 
        rx_last = rx_tail;
        rd = rx_base + rx_tail;
        rx_tail = (rx_tail + 1) % 8;
        memset(rd, 0, 16);
-       rd->buffer_addr = cpu_to_le64((u32)packet);
+       rd->buffer_addr = cpu_to_le64((unsigned long)packet);
 
        /*
         * Make sure there are no stale data in WB over this area, which
         * might get written into the memory while the e1000 also writes
         * into the same memory area.
         */
-       invalidate_dcache_range((u32)packet, (u32)packet + 4096);
+       invalidate_dcache_range((unsigned long)packet,
+                               (unsigned long)packet + 4096);
        /* Dump the DMA descriptor into RAM. */
-       flush_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1);
+       flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
        flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
        flush_dcache_range(flush_start, flush_end);
 
@@ -4955,7 +4964,7 @@ e1000_configure_tx(struct e1000_hw *hw)
        unsigned long tipg, tarc;
        uint32_t ipgr1, ipgr2;
 
-       E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
+       E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base);
        E1000_WRITE_REG(hw, TDBAH, 0);
 
        E1000_WRITE_REG(hw, TDLEN, 128);
@@ -5099,7 +5108,7 @@ e1000_configure_rx(struct e1000_hw *hw)
                E1000_WRITE_FLUSH(hw);
        }
        /* Setup the Base and Length of the Rx Descriptor Ring */
-       E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
+       E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base);
        E1000_WRITE_REG(hw, RDBAH, 0);
 
        E1000_WRITE_REG(hw, RDLEN, 128);
@@ -5130,25 +5139,26 @@ e1000_poll(struct eth_device *nic)
 {
        struct e1000_hw *hw = nic->priv;
        struct e1000_rx_desc *rd;
-       uint32_t inval_start, inval_end;
+       unsigned long inval_start, inval_end;
        uint32_t len;
 
        /* return true if there's an ethernet packet ready to read */
        rd = rx_base + rx_last;
 
        /* Re-load the descriptor from RAM. */
-       inval_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1);
+       inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
        inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
        invalidate_dcache_range(inval_start, inval_end);
 
        if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
                return 0;
-       /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
+       /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
        /* Packet received, make sure the data are re-loaded from RAM. */
        len = le32_to_cpu(rd->length);
-       invalidate_dcache_range((u32)packet,
-                               (u32)packet + roundup(len, ARCH_DMA_MINALIGN));
-       NetReceive((uchar *)packet, len);
+       invalidate_dcache_range((unsigned long)packet,
+                               (unsigned long)packet +
+                               roundup(len, ARCH_DMA_MINALIGN));
+       net_process_received_packet((uchar *)packet, len);
        fill_rx(hw);
        return 1;
 }
@@ -5162,7 +5172,7 @@ static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
        struct e1000_hw *hw = nic->priv;
        struct e1000_tx_desc *txp;
        int i = 0;
-       uint32_t flush_start, flush_end;
+       unsigned long flush_start, flush_end;
 
        txp = tx_base + tx_tail;
        tx_tail = (tx_tail + 1) % 8;
@@ -5172,10 +5182,11 @@ static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
        txp->upper.data = 0;
 
        /* Dump the packet into RAM so e1000 can pick them. */
-       flush_dcache_range((u32)nv_packet,
-                          (u32)nv_packet + roundup(length, ARCH_DMA_MINALIGN));
+       flush_dcache_range((unsigned long)nv_packet,
+                          (unsigned long)nv_packet +
+                          roundup(length, ARCH_DMA_MINALIGN));
        /* Dump the descriptor into RAM as well. */
-       flush_start = ((u32)txp) & ~(ARCH_DMA_MINALIGN - 1);
+       flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
        flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
        flush_dcache_range(flush_start, flush_end);