{
u_int16_t dummy;
- return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy));
+ return(davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy));
}
static int gen_get_link_speed(int phy_addr)
{
u_int16_t tmp;
- if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04))
+ if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
+ (tmp & 0x04)) {
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ davinci_eth_phy_read(phy_addr, PHY_ANLPAR, &tmp);
+
+ /* Speed doesn't matter, there is no setting for it in EMAC. */
+ if (tmp & (PHY_ANLPAR_TXFD | PHY_ANLPAR_10FD)) {
+ /* set EMAC for Full Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
+ &adap_emac->MACCONTROL);
+ } else {
+ /*set EMAC for Half Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE,
+ &adap_emac->MACCONTROL);
+ }
+
+ if (tmp & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+ writel(readl(&adap_emac->MACCONTROL) |
+ EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+ else
+ writel(readl(&adap_emac->MACCONTROL) &
+ ~EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+#endif
return(1);
+ }
return(0);
}
{
u_int16_t tmp;
- if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
+ if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
- tmp |= PHY_BMCR_AUTON;
- davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
+ tmp |= BMCR_ANENABLE;
+ davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
/*check AutoNegotiate complete */
udelay (10000);
- if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
+ if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return(0);
- if (!(tmp & PHY_BMSR_AUTN_COMP))
+ if (!(tmp & BMSR_ANEGCOMPLETE))
return(0);
return(gen_get_link_speed(phy_addr));
* Check if link detected is giga-bit
* If Gigabit mode detected, enable gigbit in MAC
*/
- writel(EMAC_MACCONTROL_GIGFORCE |
- EMAC_MACCONTROL_GIGABIT_ENABLE,
- &adap_emac->MACCONTROL);
+ writel(readl(&adap_emac->MACCONTROL) |
+ EMAC_MACCONTROL_GIGFORCE |
+ EMAC_MACCONTROL_GIGABIT_ENABLE,
+ &adap_emac->MACCONTROL);
}
}
}
}
#endif
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
rx_desc = emac_rx_desc;
writel(1, &adap_emac->TXCONTROL);
writel(0, &adap_ewrap->EWCTL);
#endif
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
debug_emac("- emac_close\n");
}
return -1;
memset(dev, 0, sizeof *dev);
+ sprintf(dev->name, "DaVinci-EMAC");
dev->iobase = 0;
dev->init = davinci_eth_open;
return(0);
/* Get PHY ID and initialize phy_ops for a detected PHY */
- if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) {
+ if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID1, &tmp)) {
active_phy_addr = 0xff;
return(0);
}
phy_id = (tmp << 16) & 0xffff0000;
- if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) {
+ if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID2, &tmp)) {
active_phy_addr = 0xff;
return(0);
}
phy.get_link_speed = dp83848_get_link_speed;
phy.auto_negotiate = dp83848_auto_negotiate;
break;
+ case PHY_ET1011C:
+ sprintf(phy.name, "ET1011C @ 0x%02x", active_phy_addr);
+ phy.init = gen_init_phy;
+ phy.is_phy_connected = gen_is_phy_connected;
+ phy.get_link_speed = et1011c_get_link_speed;
+ phy.auto_negotiate = gen_auto_negotiate;
+ break;
default:
sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
phy.init = gen_init_phy;