configs: Add DDR Kconfig support for Arria 10

[oweals/u-boot.git] / drivers / net / ag7xxx.c

diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index 30771b9f60d8ca34fdf9b18c5311fd974ff0190a..8146c3170e1643e293cb2e22d0e06fbed00718eb 100644 (file)
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Atheros AR71xx / AR9xxx GMAC driver
  *
  * Copyright (C) 2016 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -164,8 +163,8 @@ static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
        writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
               regs + AG7XXX_ETH_MII_MGMT_CMD);
 
-       ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
-                          AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+       ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+                               AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
        if (ret)
                return ret;
 
@@ -185,8 +184,8 @@ static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
               regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
        writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
 
-       ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
-                          AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+       ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+                               AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
 
        return ret;
 }
@@ -285,18 +284,33 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
        return 0;
 }
 
-static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
+static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
 {
        u32 data;
+       unsigned long start;
+       int ret;
+       /* No idea if this is long enough or too long */
+       int timeout_ms = 1000;
 
        /* Dummy read followed by PHY read/write command. */
-       ag7xxx_switch_reg_read(bus, 0x98, &data);
+       ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
+       if (ret < 0)
+               return ret;
        data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
-       ag7xxx_switch_reg_write(bus, 0x98, data);
+       ret = ag7xxx_switch_reg_write(bus, 0x98, data);
+       if (ret < 0)
+               return ret;
+
+       start = get_timer(0);
 
        /* Wait for operation to finish */
        do {
-               ag7xxx_switch_reg_read(bus, 0x98, &data);
+               ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
+               if (ret < 0)
+                       return ret;
+
+               if (get_timer(start) > timeout_ms)
+                       return -ETIMEDOUT;
        } while (data & BIT(31));
 
        return data & 0xffff;
@@ -310,7 +324,11 @@ static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
                             u16 val)
 {
-       ag7xxx_mdio_rw(bus, addr, reg, val);
+       int ret;
+
+       ret = ag7xxx_mdio_rw(bus, addr, reg, val);
+       if (ret < 0)
+               return ret;
        return 0;
 }
 
@@ -491,13 +509,13 @@ static void ag7xxx_eth_stop(struct udevice *dev)
 
        /* Stop the TX DMA. */
        writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
-       wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
-                    1000, 0);
+       wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
+                         1000, 0);
 
        /* Stop the RX DMA. */
        writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
-       wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
-                    1000, 0);
+       wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
+                         1000, 0);
 }
 
 /*