Please find details on the "Triple-Speed Ethernet MegaCore Function
Resource Center" of Altera.
+config BCM_SF2_ETH
+ bool "Broadcom SF2 (Starfighter2) Ethernet support"
+ select PHYLIB
+ help
+ This is an abstract framework which provides a generic interface
+ to MAC and DMA management for multiple Broadcom SoCs such as
+ Cygnus, NSP and bcm28155_ap platforms.
+
+config BCM_SF2_ETH_DEFAULT_PORT
+ int "Broadcom SF2 (Starfighter2) Ethernet default port number"
+ depends on BCM_SF2_ETH
+ default 0
+ help
+ Default port number for the Starfighter2 ethernet driver.
+
+config BCM_SF2_ETH_GMAC
+ bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support"
+ depends on BCM_SF2_ETH
+ help
+ This flag enables the ethernet support for Broadcom platforms with
+ GMAC such as Cygnus. This driver is based on the framework provided
+ by the BCM_SF2_ETH driver.
+ Say Y to any bcmcygnus based platforms.
+
config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support"
depends on DM_ETH
help
This MAC is present in Andestech SoCs.
+config MVNETA
+ bool "Marvell Armada XP/385/3700 network interface support"
+ depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
+ select PHYLIB
+ help
+ This driver supports the network interface units in the
+ Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs
+
config MVPP2
bool "Marvell Armada 375/7K/8K network interface support"
depends on ARMADA_375 || ARMADA_8K
GEM (Gigabit Ethernet MAC) found in some ARM SoC devices.
Say Y to include support for the MACB/GEM chip.
+config MACB_ZYNQ
+ bool "Cadence MACB/GEM Ethernet Interface for Xilinx Zynq"
+ depends on MACB
+ help
+ The Cadence MACB ethernet interface was used on Zynq platform.
+ Say Y to enable support for the MACB/GEM in Zynq chip.
+
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
depends on DM_ETH && DM_PCI
This driver supports Realtek 8169 series gigabit ethernet family of
PCI/PCIe chipsets/adapters.
+config SMC911X
+ bool "SMSC LAN911x and LAN921x controller driver"
+
+if SMC911X
+
+config SMC911X_BASE
+ hex "SMC911X Base Address"
+ help
+ Define this to hold the physical address
+ of the device (I/O space)
+
+choice
+ prompt "SMC911X bus width"
+ default SMC911X_16_BIT
+
+config SMC911X_32_BIT
+ bool "Enable 32-bit interface"
+
+config SMC911X_16_BIT
+ bool "Enable 16-bit interface"
+ help
+ Define this if data bus is 16 bits. If your processor
+ automatically converts one 32 bit word to two 16 bit
+ words you may also try CONFIG_SMC911X_32_BIT.
+
+endchoice
+endif #SMC911X
+
config SUN7I_GMAC
bool "Enable Allwinner GMAC Ethernet support"
help
Enable the support for Sun7i GMAC Ethernet controller
+config SUN7I_GMAC_FORCE_TXERR
+ bool "Force PA17 as gmac function"
+ depends on SUN7I_GMAC
+ help
+ Some ethernet phys needs TXERR control. Since the GMAC
+ doesn't have such signal, setting PA17 as GMAC function
+ makes the pin output low, which enables data transmission.
+
config SUN4I_EMAC
bool "Allwinner Sun4i Ethernet MAC support"
depends on DM_ETH
+ select PHYLIB
help
This driver supports the Allwinner based SUN4I Ethernet MAC.
It can be found in H3/A64/A83T based SoCs and compatible with both
External and Internal PHYs.
+config SH_ETHER
+ bool "Renesas SH Ethernet MAC"
+ select PHYLIB
+ help
+ This driver supports the Ethernet for Renesas SH and ARM SoCs.
+
config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
This driver implements support for the Ethernet AVB block in
Renesas M3 and H3 SoCs.
+config MPC8XX_FEC
+ bool "Fast Ethernet Controller on MPC8XX"
+ depends on 8xx
+ select MII
+ help
+ This driver implements support for the Fast Ethernet Controller
+ on MPC8XX
+
+config ETHER_ON_FEC1
+ bool "FEC1"
+ depends on MPC8XX_FEC
+ default y
+
+config FEC1_PHY
+ int "FEC1 PHY"
+ depends on ETHER_ON_FEC1
+ default -1
+ help
+ Define to the hardcoded PHY address which corresponds
+ to the given FEC; i. e.
+ #define CONFIG_FEC1_PHY 4
+ means that the PHY with address 4 is connected to FEC1
+
+ When set to -1, means to probe for first available.
+
+config PHY_NORXERR
+ bool "PHY_NORXERR"
+ depends on ETHER_ON_FEC1
+ default n
+ help
+ The PHY does not have a RXERR line (RMII only).
+ (so program the FEC to ignore it).
+
+config ETHER_ON_FEC2
+ bool "FEC2"
+ depends on MPC8XX_FEC && MPC885
+ default y
+
+config FEC2_PHY
+ int "FEC2 PHY"
+ depends on ETHER_ON_FEC2
+ default -1
+ help
+ Define to the hardcoded PHY address which corresponds
+ to the given FEC; i. e.
+ #define CONFIG_FEC1_PHY 4
+ means that the PHY with address 4 is connected to FEC1
+
+ When set to -1, means to probe for first available.
+
+config FEC2_PHY_NORXERR
+ bool "PHY_NORXERR"
+ depends on ETHER_ON_FEC2
+ default n
+ help
+ The PHY does not have a RXERR line (RMII only).
+ (so program the FEC to ignore it).
+
+config SYS_DPAA_QBMAN
+ bool "Device tree fixup for QBMan on freescale SOCs"
+ depends on (ARM || PPC) && !SPL_BUILD
+ default y if ARCH_B4860 || \
+ ARCH_B4420 || \
+ ARCH_P1023 || \
+ ARCH_P2041 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4240 || \
+ ARCH_T4160 || \
+ ARCH_P4080 || \
+ ARCH_P3041 || \
+ ARCH_P5040 || \
+ ARCH_P5020 || \
+ ARCH_LS1043A || \
+ ARCH_LS1046A
+ help
+ QBman fixups to allow deep sleep in DPAA 1 SOCs
+
endif # NETDEVICES