}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int read_evcr(struct spi_flash *flash, u8 *evcr)
-{
- int ret;
- const u8 cmd = CMD_READ_EVCR;
-
- ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
- if (ret < 0) {
- debug("SF: error reading EVCR\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_evcr(struct spi_flash *flash, u8 evcr)
+#ifdef CONFIG_SPI_FLASH_BAR
+/*
+ * This "clean_bar" is necessary in a situation when one was accessing
+ * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
+ *
+ * After it the BA24 bit shall be cleared to allow access to correct
+ * memory region after SW reset (by calling "reset" command).
+ *
+ * Otherwise, the BA24 bit may be left set and then after reset, the
+ * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
+ */
+static int clean_bar(struct spi_flash *flash)
{
- u8 cmd;
- int ret;
+ u8 cmd, bank_sel = 0;
- cmd = CMD_WRITE_EVCR;
- ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
- if (ret < 0) {
- debug("SF: error while writing EVCR register\n");
- return ret;
- }
+ if (flash->bank_curr == 0)
+ return 0;
+ cmd = flash->bank_write_cmd;
- return 0;
+ return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
}
-#endif
-#ifdef CONFIG_SPI_FLASH_BAR
-static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
+static int write_bar(struct spi_flash *flash, u32 offset)
{
u8 cmd, bank_sel;
int ret;
return flash->bank_curr;
}
-static int spi_flash_read_bar(struct spi_flash *flash,
- const struct spi_flash_info *info)
+static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
{
u8 curr_bank = 0;
int ret;
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
- struct spi_slave *spi = flash->spi;
-
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- spi->flags |= SPI_XFER_U_PAGE;
+ flash->flags |= SNOR_F_USE_UPAGE;
} else {
- spi->flags &= ~SPI_XFER_U_PAGE;
+ flash->flags &= ~SNOR_F_USE_UPAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
return sr && fsr;
}
-static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
- unsigned long timeout)
+static int spi_flash_wait_till_ready(struct spi_flash *flash,
+ unsigned long timeout)
{
unsigned long timebase;
int ret;
return ret;
}
- ret = spi_flash_cmd_wait_ready(flash, timeout);
+ ret = spi_flash_wait_till_ready(flash, timeout);
if (ret < 0) {
debug("SF: write %s timed out\n",
timeout == SPI_FLASH_PROG_TIMEOUT ?
spi_flash_dual(flash, &erase_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, erase_addr);
+ ret = write_bar(flash, erase_addr);
if (ret < 0)
return ret;
#endif
len -= erase_size;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(flash);
+#endif
+
return ret;
}
spi_flash_dual(flash, &write_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, write_addr);
+ ret = write_bar(flash, write_addr);
if (ret < 0)
return ret;
#endif
if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)spi->max_write_size);
+ spi->max_write_size - sizeof(cmd));
spi_flash_addr(write_addr, cmd);
offset += chunk_len;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(flash);
+#endif
+
return ret;
}
spi_flash_dual(flash, &read_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, read_addr);
+ ret = write_bar(flash, read_addr);
if (ret < 0)
return ret;
bank_sel = flash->bank_curr;
else
read_len = remain_len;
+ if (spi->max_read_size)
+ read_len = min(read_len, spi->max_read_size);
+
spi_flash_addr(read_addr, cmd);
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
data += read_len;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(flash);
+#endif
+
free(cmd);
return ret;
}
if (ret)
return ret;
- return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
}
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
break;
}
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret)
break;
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int micron_quad_enable(struct spi_flash *flash)
-{
- u8 qeb_status;
- int ret;
-
- ret = read_evcr(flash, &qeb_status);
- if (ret < 0)
- return ret;
-
- if (!(qeb_status & STATUS_QEB_MICRON))
- return 0;
-
- ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
- if (ret < 0)
- return ret;
-
- /* read EVCR and check it */
- ret = read_evcr(flash, &qeb_status);
- if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
- printf("SF: Micron EVCR Quad bit not clear\n");
- return -EINVAL;
- }
-
- return ret;
-}
-#endif
-
static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
{
int tmp;
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- return micron_quad_enable(flash);
+ debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
+ return 0;
#endif
default:
printf("SF: Need set QEB func for %02x flash\n",
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
+int spi_flash_decode_fdt(struct spi_flash *flash)
{
#ifdef CONFIG_DM_SPI_FLASH
fdt_addr_t addr;
fdt_size_t size;
- int node = flash->dev->of_offset;
- addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
+ addr = dev_read_addr_size(flash->dev, "memory-map", &size);
if (addr == FDT_ADDR_T_NONE) {
debug("%s: Cannot decode address\n", __func__);
return 0;
}
- if (flash->size != size) {
+ if (flash->size > size) {
debug("%s: Memory map must cover entire device\n", __func__);
return -1;
}
{
struct spi_slave *spi = flash->spi;
const struct spi_flash_info *info = NULL;
- int ret = -1;
+ int ret;
info = spi_flash_read_id(flash);
if (IS_ERR_OR_NULL(info))
return -ENOENT;
- /* Flash powers up read-only, so clear BP# bits */
+ /*
+ * Flash powers up read-only, so clear BP# bits.
+ *
+ * Note on some flash (like Macronix), QE (quad enable) bit is in the
+ * same status register as BP# bits, and we need preserve its original
+ * value during a reboot cycle as this is required by some platforms
+ * (like Intel ICH SPI controller working under descriptor mode).
+ */
if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
- JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
- JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
- write_sr(flash, 0);
+ (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
+ (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
+ u8 sr = 0;
+
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
+ read_sr(flash, &sr);
+ sr &= STATUS_QEB_MXIC;
+ }
+ write_sr(flash, sr);
+ }
- /* Assign spi data */
flash->name = info->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = spi->option;
- /* Assign spi flash flags */
if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
- /* Assign spi_flash ops */
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_read_bar(flash, info);
+ ret = read_bar(flash, info);
if (ret < 0)
return ret;
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- ret = spi_flash_decode_fdt(gd->fdt_blob, flash);
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = spi_flash_decode_fdt(flash);
if (ret) {
debug("SF: FDT decode error\n");
return -EINVAL;
}
#endif
- return ret;
+ return 0;
}
projects / oweals / u-boot.git / blobdiff