mtd: spi: Switch to new SPI NOR framework

[oweals/u-boot.git] / drivers / mtd / spi / spi-nor-core.c

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 13c6236d623abb150fc9e8ecacd3cde6b9691bb2..7590ff7716e86f6d9dc40aa820242d8ad122cf66 100644 (file)
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -21,6 +21,8 @@
 #include <spi-mem.h>
 #include <spi.h>
 
+#include "sf_internal.h"
+
 /* Define max times to check status register before we give up. */
 
 /*
@@ -32,63 +34,6 @@
 
 #define DEFAULT_READY_WAIT_JIFFIES             (40UL * HZ)
 
-#define SPI_NOR_MAX_ID_LEN     6
-#define SPI_NOR_MAX_ADDR_WIDTH 4
-
-struct flash_info {
-       char            *name;
-
-       /*
-        * This array stores the ID bytes.
-        * The first three bytes are the JEDIC ID.
-        * JEDEC ID zero means "no ID" (mostly older chips).
-        */
-       u8              id[SPI_NOR_MAX_ID_LEN];
-       u8              id_len;
-
-       /* The size listed here is what works with SPINOR_OP_SE, which isn't
-        * necessarily called a "sector" by the vendor.
-        */
-       unsigned int    sector_size;
-       u16             n_sectors;
-
-       u16             page_size;
-       u16             addr_width;
-
-       u16             flags;
-#define SECT_4K                        BIT(0)  /* SPINOR_OP_BE_4K works uniformly */
-#define SPI_NOR_NO_ERASE       BIT(1)  /* No erase command needed */
-#define SST_WRITE              BIT(2)  /* use SST byte programming */
-#define SPI_NOR_NO_FR          BIT(3)  /* Can't do fastread */
-#define SECT_4K_PMC            BIT(4)  /* SPINOR_OP_BE_4K_PMC works uniformly */
-#define SPI_NOR_DUAL_READ      BIT(5)  /* Flash supports Dual Read */
-#define SPI_NOR_QUAD_READ      BIT(6)  /* Flash supports Quad Read */
-#define USE_FSR                        BIT(7)  /* use flag status register */
-#define SPI_NOR_HAS_LOCK       BIT(8)  /* Flash supports lock/unlock via SR */
-#define SPI_NOR_HAS_TB         BIT(9)  /*
-                                        * Flash SR has Top/Bottom (TB) protect
-                                        * bit. Must be used with
-                                        * SPI_NOR_HAS_LOCK.
-                                        */
-#define        SPI_S3AN                BIT(10) /*
-                                        * Xilinx Spartan 3AN In-System Flash
-                                        * (MFR cannot be used for probing
-                                        * because it has the same value as
-                                        * ATMEL flashes)
-                                        */
-#define SPI_NOR_4B_OPCODES     BIT(11) /*
-                                        * Use dedicated 4byte address op codes
-                                        * to support memory size above 128Mib.
-                                        */
-#define NO_CHIP_ERASE          BIT(12) /* Chip does not support chip erase */
-#define SPI_NOR_SKIP_SFDP      BIT(13) /* Skip parsing of SFDP tables */
-#define USE_CLSR               BIT(14) /* use CLSR command */
-
-       int     (*quad_enable)(struct spi_nor *nor);
-};
-
-#define JEDEC_MFR(info)        ((info)->id[0])
-
 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
                *op, void *buf)
 {