Merge git://git.denx.de/u-boot-sunxi

[oweals/u-boot.git] / drivers / mtd / spi / sf_internal.h

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index cde4cfbf2e32b5b1257b2d5a9b2b44080dc496ec..614a293234e074faf5e5b300974a85c6bfbccad0 100644 (file)
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -23,6 +23,7 @@ enum spi_dual_flash {
 enum spi_nor_option_flags {
        SNOR_F_SST_WR           = BIT(0),
        SNOR_F_USE_FSR          = BIT(1),
+       SNOR_F_USE_UPAGE        = BIT(3),
 };
 
 #define SPI_FLASH_3B_ADDR_LEN          3
@@ -48,7 +49,6 @@ enum spi_nor_option_flags {
 #define CMD_WRITE_DISABLE              0x04
 #define CMD_WRITE_ENABLE               0x06
 #define CMD_QUAD_PAGE_PROGRAM          0x32
-#define CMD_WRITE_EVCR                 0x61
 
 /* Read commands */
 #define CMD_READ_ARRAY_SLOW            0x03
@@ -62,7 +62,6 @@ enum spi_nor_option_flags {
 #define CMD_READ_STATUS1               0x35
 #define CMD_READ_CONFIG                        0x35
 #define CMD_FLAG_STATUS                        0x70
-#define CMD_READ_EVCR                  0x65
 
 /* Bank addr access commands */
 #ifdef CONFIG_SPI_FLASH_BAR
@@ -77,7 +76,6 @@ enum spi_nor_option_flags {
 #define STATUS_QEB_WINSPAN             BIT(1)
 #define STATUS_QEB_MXIC                        BIT(6)
 #define STATUS_PEC                     BIT(7)
-#define STATUS_QEB_MICRON              BIT(7)
 #define SR_BP0                         BIT(2)  /* Block protect 0 */
 #define SR_BP1                         BIT(3)  /* Block protect 1 */
 #define SR_BP2                         BIT(4)  /* Block protect 2 */
@@ -89,6 +87,19 @@ enum spi_nor_option_flags {
 
 /* SST specific */
 #ifdef CONFIG_SPI_FLASH_SST
+#define SST26_CMD_READ_BPR             0x72
+#define SST26_CMD_WRITE_BPR            0x42
+
+#define SST26_BPR_8K_NUM               4
+#define SST26_MAX_BPR_REG_LEN          (18 + 1)
+#define SST26_BOUND_REG_SIZE           ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
+
+enum lock_ctl {
+       SST26_CTL_LOCK,
+       SST26_CTL_UNLOCK,
+       SST26_CTL_CHECK
+};
+
 # define CMD_SST_BP            0x02    /* Byte Program */
 # define CMD_SST_AAI_WP                0xAD    /* Auto Address Incr Word Program */
 
@@ -98,42 +109,45 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
                const void *buf);
 #endif
 
-#ifdef CONFIG_SPI_FLASH_SPANSION
-/* Used for Spansion S25FS-S family flash only. */
-#define CMD_SPANSION_RDAR      0x65 /* Read any device register */
-#define CMD_SPANSION_WRAR      0x71 /* Write any device register */
-#endif
-/**
- * struct spi_flash_params - SPI/QSPI flash device params structure
- *
- * @name:              Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec:             Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec:         Device ext_jedec ID
- * @sector_size:       Isn't necessarily a sector size from vendor,
- *                     the size listed here is what works with CMD_ERASE_64K
- * @nr_sectors:                No.of sectors on this device
- * @flags:             Important param, for flash specific behaviour
- */
-struct spi_flash_params {
-       const char *name;
-       u32 jedec;
-       u16 ext_jedec;
-       u32 sector_size;
-       u32 nr_sectors;
-
-       u16 flags;
-#define SECT_4K                        BIT(0)
-#define E_FSR                  BIT(1)
-#define SST_WR                 BIT(2)
-#define WR_QPP                 BIT(3)
-#define RD_QUAD                        BIT(4)
-#define RD_DUAL                        BIT(5)
-#define RD_QUADIO              BIT(6)
-#define RD_DUALIO              BIT(7)
+#define JEDEC_MFR(info)                ((info)->id[0])
+#define JEDEC_ID(info)         (((info)->id[1]) << 8 | ((info)->id[2]))
+#define JEDEC_EXT(info)                (((info)->id[3]) << 8 | ((info)->id[4]))
+#define SPI_FLASH_MAX_ID_LEN   6
+
+struct spi_flash_info {
+       /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */
+       const char      *name;
+
+       /*
+        * This array stores the ID bytes.
+        * The first three bytes are the JEDIC ID.
+        * JEDEC ID zero means "no ID" (mostly older chips).
+        */
+       u8              id[SPI_FLASH_MAX_ID_LEN];
+       u8              id_len;
+
+       /*
+        * The size listed here is what works with SPINOR_OP_SE, which isn't
+        * necessarily called a "sector" by the vendor.
+        */
+       u32             sector_size;
+       u32             n_sectors;
+
+       u16             page_size;
+
+       u16             flags;
+#define SECT_4K                        BIT(0)  /* CMD_ERASE_4K works uniformly */
+#define E_FSR                  BIT(1)  /* use flag status register for */
+#define SST_WR                 BIT(2)  /* use SST byte/word programming */
+#define WR_QPP                 BIT(3)  /* use Quad Page Program */
+#define RD_QUAD                        BIT(4)  /* use Quad Read */
+#define RD_DUAL                        BIT(5)  /* use Dual Read */
+#define RD_QUADIO              BIT(6)  /* use Quad IO Read */
+#define RD_DUALIO              BIT(7)  /* use Dual IO Read */
 #define RD_FULL                        (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO)
 };
 
-extern const struct spi_flash_params spi_flash_params_table[];
+extern const struct spi_flash_info spi_flash_ids[];
 
 /* Send a single-byte command to the device and read the response */
 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
@@ -182,7 +196,7 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
  * - SPI claim
  * - spi_flash_cmd_write_enable
  * - spi_flash_cmd_write
- * - spi_flash_cmd_wait_ready
+ * - spi_flash_wait_till_ready
  * - SPI release
  */
 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,