mtd: nand: Wait for PAGEPROG to finish in drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS

[oweals/u-boot.git] / drivers / mtd / nand / fsmc_nand.c

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 7a61d88cc573232b2530159d7725505c34fd8eb0..d5d105629369a5ae0def96fc3227e774c09a03ea 100644 (file)
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -5,23 +5,7 @@
  * (C) Copyright 2012
  * Amit Virdi, ST Microelectronics, amit.virdi@st.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -181,7 +165,7 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
 
 static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
 {
-       struct nand_chip *this = mtd->priv;
+       struct nand_chip *this = mtd_to_nand(mtd);
        ulong IO_ADDR_W;
 
        if (ctrl & NAND_CTRL_CHANGE) {
@@ -341,6 +325,7 @@ void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
  * @mtd:       mtd info structure
  * @chip:      nand chip info structure
  * @buf:       buffer to store read data
+ * @oob_required:      caller expects OOB data read to chip->oob_poi
  * @page:      page number to read
  *
  * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
@@ -350,7 +335,7 @@ void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
  * max of 8 bits)
  */
 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-                                uint8_t *buf, int page)
+                                uint8_t *buf, int oob_required, int page)
 {
        struct fsmc_eccplace *fsmc_eccpl;
        int i, j, s, stat, eccsize = chip->ecc.size;
@@ -405,11 +390,59 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
        return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsmc_nand_switch_ecc - switch the ECC operation between different engines
+ *
+ * @eccstrength                - the number of bits that could be corrected
+ *                       (1 - HW, 4 - SW BCH4)
+ */
+int fsmc_nand_switch_ecc(uint32_t eccstrength)
+{
+       struct nand_chip *nand;
+       struct mtd_info *mtd;
+       int err;
+
+       /*
+        * This functions is only called on SPEAr600 platforms, supporting
+        * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
+        * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
+        * function, as it doesn't need to switch to a different ECC layout.
+        */
+       mtd = get_nand_dev_by_index(nand_curr_device);
+       nand = mtd_to_nand(mtd);
+
+       /* Setup the ecc configurations again */
+       if (eccstrength == 1) {
+               nand->ecc.mode = NAND_ECC_HW;
+               nand->ecc.bytes = 3;
+               nand->ecc.strength = 1;
+               nand->ecc.layout = &fsmc_ecc1_layout;
+               nand->ecc.calculate = fsmc_read_hwecc;
+               nand->ecc.correct = nand_correct_data;
+       } else if (eccstrength == 4) {
+               /*
+                * .calculate .correct and .bytes will be set in
+                * nand_scan_tail()
+                */
+               nand->ecc.mode = NAND_ECC_SOFT_BCH;
+               nand->ecc.strength = 4;
+               nand->ecc.layout = NULL;
+       } else {
+               printf("Error: ECC strength %d not supported!\n", eccstrength);
+       }
+
+       /* Update NAND handling after ECC mode switch */
+       err = nand_scan_tail(mtd);
+
+       return err;
+}
+#endif /* CONFIG_SPL_BUILD */
+
 int fsmc_nand_init(struct nand_chip *nand)
 {
        static int chip_nr;
        struct mtd_info *mtd;
-       int i;
        u32 peripid2 = readl(&fsmc_regs_p->peripid2);
 
        fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
@@ -446,12 +479,12 @@ int fsmc_nand_init(struct nand_chip *nand)
                (void  __iomem *)CONFIG_SYS_NAND_BASE;
        nand->badblockbits = 7;
 
-       mtd = &nand_info[chip_nr++];
-       mtd->priv = nand;
+       mtd = nand_to_mtd(nand);
 
        switch (fsmc_version) {
        case FSMC_VER8:
                nand->ecc.bytes = 13;
+               nand->ecc.strength = 8;
                nand->ecc.correct = fsmc_bch8_correct_data;
                nand->ecc.read_page = fsmc_read_page_hwecc;
                if (mtd->writesize == 512)
@@ -466,6 +499,7 @@ int fsmc_nand_init(struct nand_chip *nand)
                break;
        default:
                nand->ecc.bytes = 3;
+               nand->ecc.strength = 1;
                nand->ecc.layout = &fsmc_ecc1_layout;
                nand->ecc.correct = nand_correct_data;
                break;
@@ -478,9 +512,8 @@ int fsmc_nand_init(struct nand_chip *nand)
        if (nand_scan_tail(mtd))
                return -ENXIO;
 
-       for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-               if (nand_register(i))
-                       return -ENXIO;
+       if (nand_register(chip_nr++, mtd))
+               return -ENXIO;
 
        return 0;
 }