cfi_flash: Fix logical continuations

[oweals/u-boot.git] / drivers / mtd / nand / fsmc_nand.c

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 0976a67ff8383678bfc4447d4a9f810d57366ec4..d5d105629369a5ae0def96fc3227e774c09a03ea 100644 (file)
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <linux/bitops.h>
 #include <linux/err.h>
-#include <linux/mtd/nand_bch.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
@@ -166,7 +165,7 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
 
 static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
 {
-       struct nand_chip *this = mtd->priv;
+       struct nand_chip *this = mtd_to_nand(mtd);
        ulong IO_ADDR_W;
 
        if (ctrl & NAND_CTRL_CHANGE) {
@@ -398,14 +397,20 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @eccstrength                - the number of bits that could be corrected
  *                       (1 - HW, 4 - SW BCH4)
  */
-int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)
+int fsmc_nand_switch_ecc(uint32_t eccstrength)
 {
        struct nand_chip *nand;
        struct mtd_info *mtd;
        int err;
 
-       mtd = &nand_info[nand_curr_device];
-       nand = mtd->priv;
+       /*
+        * This functions is only called on SPEAr600 platforms, supporting
+        * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
+        * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
+        * function, as it doesn't need to switch to a different ECC layout.
+        */
+       mtd = get_nand_dev_by_index(nand_curr_device);
+       nand = mtd_to_nand(mtd);
 
        /* Setup the ecc configurations again */
        if (eccstrength == 1) {
@@ -413,14 +418,18 @@ int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)
                nand->ecc.bytes = 3;
                nand->ecc.strength = 1;
                nand->ecc.layout = &fsmc_ecc1_layout;
+               nand->ecc.calculate = fsmc_read_hwecc;
                nand->ecc.correct = nand_correct_data;
-       } else {
+       } else if (eccstrength == 4) {
+               /*
+                * .calculate .correct and .bytes will be set in
+                * nand_scan_tail()
+                */
                nand->ecc.mode = NAND_ECC_SOFT_BCH;
-               nand->ecc.calculate = nand_bch_calculate_ecc;
-               nand->ecc.correct = nand_bch_correct_data;
-               nand->ecc.bytes = 7;
                nand->ecc.strength = 4;
                nand->ecc.layout = NULL;
+       } else {
+               printf("Error: ECC strength %d not supported!\n", eccstrength);
        }
 
        /* Update NAND handling after ECC mode switch */
@@ -434,7 +443,6 @@ int fsmc_nand_init(struct nand_chip *nand)
 {
        static int chip_nr;
        struct mtd_info *mtd;
-       int i;
        u32 peripid2 = readl(&fsmc_regs_p->peripid2);
 
        fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
@@ -471,8 +479,7 @@ int fsmc_nand_init(struct nand_chip *nand)
                (void  __iomem *)CONFIG_SYS_NAND_BASE;
        nand->badblockbits = 7;
 
-       mtd = &nand_info[chip_nr++];
-       mtd->priv = nand;
+       mtd = nand_to_mtd(nand);
 
        switch (fsmc_version) {
        case FSMC_VER8:
@@ -505,9 +512,8 @@ int fsmc_nand_init(struct nand_chip *nand)
        if (nand_scan_tail(mtd))
                return -ENXIO;
 
-       for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-               if (nand_register(i))
-                       return -ENXIO;
+       if (nand_register(chip_nr++, mtd))
+               return -ENXIO;
 
        return 0;
 }