mtd: nand: add generic helpers to check, match, maximize ECC settings

[oweals/u-boot.git] / drivers / mtd / nand / atmel_nand.c

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index a81b96d28136f3f41979a688a2b25fed95235e23..65dd83eced5860ddbecf5a062867b2cc32a212c8 100644 (file)
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -24,9 +24,9 @@
 
 /* Register access macros */
 #define ecc_readl(add, reg)                            \
-       readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+       readl(add + ATMEL_ECC_##reg)
 #define ecc_writel(add, reg, value)                    \
-       writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+       writel((value), add + ATMEL_ECC_##reg)
 
 #include "atmel_nand_ecc.h"    /* Hardware ECC registers */
 
@@ -513,7 +513,7 @@ normal_check:
                        if (err_nbr == -1) {
                                dev_err(host->dev, "PMECC: Too many errors\n");
                                mtd->ecc_stats.failed++;
-                               return -EIO;
+                               return -EBADMSG;
                        } else {
                                pmecc_correct_data(mtd, buf_pos, ecc, i,
                                        host->pmecc_bytes_per_sector, err_nbr);
@@ -562,7 +562,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
        stat = pmecc_readl(host->pmecc, isr);
        if (stat != 0)
                if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
-                       return -EIO;
+                       return -EBADMSG;
 
        return 0;
 }
@@ -702,7 +702,7 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
        if (chip->onfi_version) {
                *cap = chip->ecc_strength_ds;
                *sector_size = chip->ecc_step_ds;
-               MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
+               pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
                         *cap, *sector_size);
        }
 
@@ -863,9 +863,8 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
                host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 #endif
 
-       MTDDEBUG(MTD_DEBUG_LEVEL1,
-               "Initialize PMECC params, cap: %d, sector: %d\n",
-               cap, sector_size);
+       pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
+                cap, sector_size);
 
        host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
        host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
@@ -1112,7 +1111,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
                 * We can't correct so many errors */
                dev_warn(host->dev, "atmel_nand : multiple errors detected."
                                " Unable to correct.\n");
-               return -EIO;
+               return -EBADMSG;
        }
 
        /* if there's a single bit error : we can correct it */
@@ -1156,6 +1155,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
        nand->ecc.hwctl = atmel_nand_hwctl;
        nand->ecc.read_page = atmel_nand_read_page;
        nand->ecc.bytes = 4;
+       nand->ecc.strength = 4;
 
        if (nand->ecc.mode == NAND_ECC_HW) {
                /* ECC is calculated for the whole page (1 step) */
@@ -1221,7 +1221,8 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
                        IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
 
 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
-               gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
+               at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+                                   !(ctrl & NAND_NCE));
 #endif
                this->IO_ADDR_W = (void *) IO_ADDR_W;
        }
@@ -1233,7 +1234,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
 #ifdef CONFIG_SYS_NAND_READY_PIN
 static int at91_nand_ready(struct mtd_info *mtd)
 {
-       return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
+       return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
 }
 #endif
 
@@ -1378,34 +1379,6 @@ static int nand_read_page(int block, int page, void *dst)
 }
 #endif /* CONFIG_SPL_NAND_ECC */
 
-int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
-{
-       unsigned int block, lastblock;
-       unsigned int page;
-
-       block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
-       lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
-       page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
-
-       while (block <= lastblock) {
-               if (!nand_is_bad_block(block)) {
-                       while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
-                               nand_read_page(block, page, dst);
-                               dst += CONFIG_SYS_NAND_PAGE_SIZE;
-                               page++;
-                       }
-
-                       page = 0;
-               } else {
-                       lastblock++;
-               }
-
-               block++;
-       }
-
-       return 0;
-}
-
 int at91_nand_wait_ready(struct mtd_info *mtd)
 {
        struct nand_chip *this = mtd_to_nand(mtd);
@@ -1448,7 +1421,7 @@ int board_nand_init(struct nand_chip *nand)
 
 void nand_init(void)
 {
-       mtd = &nand_chip.mtd;
+       mtd = nand_to_mtd(&nand_chip);
        mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
        mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
        nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
@@ -1472,6 +1445,8 @@ void nand_deselect(void)
                nand_chip.select_chip(mtd, -1);
 }
 
+#include "nand_spl_loaders.c"
+
 #else
 
 #ifndef CONFIG_SYS_NAND_BASE_LIST