Merge branch 'next' of ../next

[oweals/u-boot.git] / drivers / mmc / tegra2_mmc.h

diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h
index 28698e0fc0a29ed9b86218119d3449d2744507e7..b2f6c5baad059c81479f83fb9f9a187d2cf162fa 100644 (file)
--- a/drivers/mmc/tegra2_mmc.h
+++ b/drivers/mmc/tegra2_mmc.h
@@ -68,15 +68,66 @@ struct tegra2_mmc {
        unsigned char   res6[0x100];    /* RESERVED, offset 100h-1FFh */
 };
 
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK                          (3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                          (0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                   (2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT                   (3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE                            (1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE                    (1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE               (0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ                        (1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT                    (1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK                 (3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE          (0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136           (1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48            (2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY       (3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK                         (1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK                       (1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER     (1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD                       (1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT                       (1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE                 (1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE                 (1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE                       (1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT                  8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK                   (0xff << 8)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL                       (1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE                  (1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE                  (1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE                       (1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE                      (1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT                      (1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT                      (1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT                                (1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE                     (1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE                    (1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT                    (1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY               (1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY                        (1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                    (1 << 1)
+
 struct mmc_host {
        struct tegra2_mmc *reg;
        unsigned int version;   /* SDHCI spec. version */
        unsigned int clock;     /* Current clock (MHz) */
        unsigned int base;      /* Base address, SDMMC1/2/3/4 */
        enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
+       int pwr_gpio;           /* Power GPIO */
+       int cd_gpio;            /* Change Detect GPIO */
 };
 
-int tegra2_mmc_init(int dev_index, int bus_width);
+int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __TEGRA2_MMC_H_ */