cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
if (cd_pin >= 0) {
ret = gpio_request(cd_pin, "mmc_cd");
- if (!ret)
+ if (!ret) {
+ sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
ret = gpio_direction_input(cd_pin);
+ }
}
return ret;
/* determine delays */
if (hz <= 400000) {
oclk_dly = 0;
- sclk_dly = 7;
+ sclk_dly = 0;
} else if (hz <= 25000000) {
oclk_dly = 0;
sclk_dly = 5;
+#ifdef CONFIG_MACH_SUN9I
} else if (hz <= 50000000) {
- oclk_dly = 3;
- sclk_dly = 5;
+ oclk_dly = 5;
+ sclk_dly = 4;
} else {
/* hz > 50000000 */
oclk_dly = 2;
sclk_dly = 4;
+#else
+ } else if (hz <= 50000000) {
+ oclk_dly = 3;
+ sclk_dly = 4;
+ } else {
+ /* hz > 50000000 */
+ oclk_dly = 1;
+ sclk_dly = 4;
+#endif
}
writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
return 0;
}
-static void sunxi_mmc_set_ios(struct mmc *mmc)
+static int sunxi_mmc_set_ios(struct mmc *mmc)
{
struct sunxi_mmc_host *mmchost = mmc->priv;
/* Change clock first */
if (mmc->clock && mmc_config_clock(mmc) != 0) {
mmchost->fatal_err = 1;
- return;
+ return -EINVAL;
}
/* Change bus width */
writel(0x1, &mmchost->reg->width);
else
writel(0x0, &mmchost->reg->width);
+
+ return 0;
}
static int sunxi_mmc_core_init(struct mmc *mmc)
const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
SUNXI_MMC_STATUS_FIFO_FULL;
unsigned i;
- unsigned byte_cnt = data->blocksize * data->blocks;
- unsigned timeout_msecs = 2000;
unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
+ unsigned byte_cnt = data->blocksize * data->blocks;
+ unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
+ if (timeout_usecs < 2000000)
+ timeout_usecs = 2000000;
/* Always read / write data through the CPU */
setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
for (i = 0; i < (byte_cnt >> 2); i++) {
while (readl(&mmchost->reg->status) & status_bit) {
- if (!timeout_msecs--)
+ if (!timeout_usecs--)
return -1;
- udelay(1000);
+ udelay(1);
}
if (reading)
(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
debug("%s timeout %x\n", what,
status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
- return TIMEOUT;
+ return -ETIMEDOUT;
}
udelay(1000);
} while (!(status & done_bit));
cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
if (data) {
- if ((u32) data->dest & 0x3) {
+ if ((u32)(long)data->dest & 0x3) {
error = -1;
goto out;
}
if (ret) {
error = readl(&mmchost->reg->rint) & \
SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
- error = TIMEOUT;
+ error = -ETIMEDOUT;
goto out;
}
}
status = readl(&mmchost->reg->status);
if (!timeout_msecs--) {
debug("busy timeout\n");
- error = TIMEOUT;
+ error = -ETIMEDOUT;
goto out;
}
udelay(1000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
+ if (sdc_no == 2)
+ cfg->host_caps = MMC_MODE_8BIT;
+#endif
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;