Merge tag 'mips-updates-for-2019.11' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / drivers / mmc / sunxi_mmc.c

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 147eb9b4d5f9c3c49f92a414b85c7ee4442da5c3..9bf040cb40871fdc3e730549dd5396f9c192d8e0 100644 (file)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -98,24 +98,21 @@ static int mmc_resource_init(int sdc_no)
 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
        unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
-       bool new_mode = false;
+       bool new_mode = true;
        bool calibrate = false;
        u32 val = 0;
 
-       if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
-               new_mode = true;
+       if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
+               new_mode = false;
+
+       /* A83T support new mode only on eMMC */
+       if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
+               new_mode = false;
 
 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
        calibrate = true;
 #endif
 
-       /*
-        * The MMC clock has an extra /2 post-divider when operating in the new
-        * mode.
-        */
-       if (new_mode)
-               hz = hz * 2;
-
        if (hz <= 24000000) {
                pll = CCM_MMC_CTRL_OSCM24;
                pll_hz = 24000000;
@@ -176,7 +173,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 
        if (new_mode) {
 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
                val = CCM_MMC_CTRL_MODE_SEL_NEW;
+#endif
                setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 #endif
        } else if (!calibrate) {