Merge branch 'master' of git://git.denx.de/u-boot-spi

[oweals/u-boot.git] / drivers / mmc / sunxi_mmc.c

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index fe6d82c7b4eb4a3f2aac900b15eef3296008b805..9bf040cb40871fdc3e730549dd5396f9c192d8e0 100644 (file)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -70,10 +70,12 @@ static int mmc_resource_init(int sdc_no)
                priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
                priv->mclkreg = &ccm->sd2_clk_cfg;
                break;
+#ifdef SUNXI_MMC3_BASE
        case 3:
                priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
                priv->mclkreg = &ccm->sd3_clk_cfg;
                break;
+#endif
        default:
                printf("Wrong mmc number %d\n", sdc_no);
                return -1;
@@ -96,18 +98,20 @@ static int mmc_resource_init(int sdc_no)
 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
        unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
-       bool new_mode = false;
+       bool new_mode = true;
+       bool calibrate = false;
        u32 val = 0;
 
-       if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
-               new_mode = true;
+       if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
+               new_mode = false;
 
-       /*
-        * The MMC clock has an extra /2 post-divider when operating in the new
-        * mode.
-        */
-       if (new_mode)
-               hz = hz * 2;
+       /* A83T support new mode only on eMMC */
+       if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
+               new_mode = false;
+
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
+       calibrate = true;
+#endif
 
        if (hz <= 24000000) {
                pll = CCM_MMC_CTRL_OSCM24;
@@ -116,6 +120,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 #ifdef CONFIG_MACH_SUN9I
                pll = CCM_MMC_CTRL_PLL_PERIPH0;
                pll_hz = clock_get_pll4_periph0();
+#elif defined(CONFIG_MACH_SUN50I_H6)
+               pll = CCM_MMC_CTRL_PLL6X2;
+               pll_hz = clock_get_pll6() * 2;
 #else
                pll = CCM_MMC_CTRL_PLL6;
                pll_hz = clock_get_pll6();
@@ -166,10 +173,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 
        if (new_mode) {
 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
                val = CCM_MMC_CTRL_MODE_SEL_NEW;
+#endif
                setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 #endif
-       } else {
+       } else if (!calibrate) {
+               /*
+                * Use hardcoded delay values if controller doesn't support
+                * calibration
+                */
                val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
                        CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
        }
@@ -223,6 +236,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
        rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
        writel(rval, &priv->reg->clkcr);
 
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
+       /* A64 supports calibration of delays on MMC controller and we
+        * have to set delay of zero before starting calibration.
+        * Allwinner BSP driver sets a delay only in the case of
+        * using HS400 which is not supported by mainline U-Boot or
+        * Linux at the moment
+        */
+       writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
+#endif
+
        /* Re-enable Clock */
        rval |= SUNXI_MMC_CLK_ENABLE;
        writel(rval, &priv->reg->clkcr);
@@ -494,7 +517,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 
        cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
        cfg->host_caps = MMC_MODE_4BIT;
-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
        if (sdc_no == 2)
                cfg->host_caps = MMC_MODE_8BIT;
 #endif
@@ -509,6 +532,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 
        /* config ahb clock */
        debug("init mmc %d clock and io\n", sdc_no);
+#if !defined(CONFIG_MACH_SUN50I_H6)
        setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
 #ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -519,6 +543,11 @@ struct mmc *sunxi_mmc_init(int sdc_no)
        /* sun9i has a mmc-common module, also set the gate and reset there */
        writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
               SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
+#else /* CONFIG_MACH_SUN50I_H6 */
+       setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
+       /* unassert reset */
+       setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
 #endif
        ret = mmc_set_mod_clk(priv, 24000000);
        if (ret)
@@ -637,7 +666,9 @@ static int sunxi_mmc_bind(struct udevice *dev)
 }
 
 static const struct udevice_id sunxi_mmc_ids[] = {
+       { .compatible = "allwinner,sun4i-a10-mmc" },
        { .compatible = "allwinner,sun5i-a13-mmc" },
+       { .compatible = "allwinner,sun7i-a20-mmc" },
        { }
 };